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dc.contributor.author林煜翔en_US
dc.contributor.authorLin, Yu-Hsiangen_US
dc.contributor.author陳明哲en_US
dc.contributor.authorChen, Ming-Jeren_US
dc.date.accessioned2014-12-12T01:46:19Z-
dc.date.available2014-12-12T01:46:19Z-
dc.date.issued2012en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079811527en_US
dc.identifier.urihttp://hdl.handle.net/11536/46708-
dc.description.abstract  在體積更小、更快、更省電等等便利性和經濟性的訴求下,電子元件尺寸的微縮便成為了未來的趨勢。而隨著電子元件尺寸的微縮,奈米尺度的隨機擾動電子訊號(RTS, Random Telegraph Signals)也因而越來越不可忽視。因此,研究小尺寸元件中RTS對元件電性所帶來的影響便成為了一門重要的課題。RTS現象的發生普遍認為是載子被氧化層中的缺陷重複進行捕捉-釋放的過程。當載子被捕捉時,被捕捉的載子會在氧化層中產生一股額外的屏蔽庫侖電位,它將影響到通道中的載子,使得汲極╱源極的電流大小隨著捕捉-釋放的過程而在兩個階段間波動。在實驗中,我們較不容易觀察到汲極╱源極的電流變化量和這些可能影響RTS的參數之間的關係。其中一個理由是,我們無法自由地改變實際的元件的各項參數以改變其物理特性,而另一個理由則是,我們難以在一片晶片上找到足夠多具有RTS現象的元件。然而, TCAD模擬使得我們能夠解決這些問題。在TCAD模擬中,我們可以藉由設定我們所需要的參數,像是閘極長度、閘極寬度、摻雜濃度等等來控制元件的特性,並且可以插入一個缺陷到矽氧化層中以確保此結構具有RTS的現象。   本篇論文的主要目標是建立一個新穎的RTS物理模型。而在建立模型之前,我們須先量測實際的實驗數據,再佐以TCAD的模擬來了解RTS的各種特性。首先,藉由TCAD的模擬,我們調整了MOSFET尺寸的大小、trap的大小、以及trap的位置。經由比較汲極╱源極電流變化量和各種參數間的變化關係,我們能夠得出隨參數變化而導致的電流變化趨勢:(1)汲極電流變化率會隨著元件尺寸的漸小而漸增;(2) 汲極電流變化率的曲線圖上會有一個最大值同時也是曲線的轉折點,而此轉折點的轉折程度會隨著元件尺寸的漸小而逐漸變得劇烈;(3)當兩個元件有同樣閘極寬度時,汲極電流變化率曲線在次臨界電壓區域時的斜率也會一樣;(4)缺陷在閘極正中央的汲極╱源極電流會比缺陷在閘極邊緣的汲極╱源極電流來得小;(5)缺陷靠近源極的汲極╱源極電流會比缺陷靠近汲極的汲極╱源極電流來得小。   接下來在分析過模擬結果之後,我們假設當元件在次臨界電壓時,於相同的閘極偏壓下,汲極電流變化率將只和元件寬度有關( )而並非同時與元件寬度以及長度有關( )。藉由從模型求出的缺陷尺寸來驗證模擬跑出來的缺陷尺寸、以及由模擬跑出來的缺陷尺寸來驗證模型求出的缺陷尺寸兩個相反的方式,可以證明這個假設。以此結果為根據,將 和 兩個模型藉由波茲曼函數合併起來,使得我們的新模型在次臨界電壓區域有 的特性、在強反轉區域有 的特性。並且,為了使此模型能夠應用在實際數據,我們適當地將其簡化。zh_TW
dc.description.abstractDue to the request for smaller, faster, and more efficient metal-oxide-semiconductor field-effect transistors (MOSFETs), down-scaling has become a current trend of device development. As the dimensions of device are scaled, random telegraph signals (RTS) play an important role in the development of scaling technologies. Hence, researching the electronic property in the presence of RTS in nano-scale devices is becoming a challenging issue. These signals are generally considered as carrier trapping-detrapping from a defect situated in the silicon oxide. When a carrier is trapped, the trapped carrier will produce an additional screened Coulomb potential in the silicon oxide affecting the carriers in channel, and it makes the drain/source current fluctuate between two discrete levels as a trapping-detrapping process. In the experiment, it is not easy to observe the relation between drain/source current variation and the parameters which may impact RTS phenomenon. The one reason is that we cannot modify the characteristic of real devices as we want, and the other reason is that it is difficult to find RTS events across the whole wafer. However, we can solve these problems by using TCAD simulation. In TCAD simulation, we can control the device characteristics by setting any parameters such as gate length, gate width, and doping concentrate, and insert a trap into silicon oxide to make sure the occurrence of RTS events in structure. Building a new physical model of RTS is the major purpose in this thesis. Before building it, we have to characterize the practical device to get experimental data, and analyze its identity by simulating RTS phenomenon by TCAD. First, we built a MOSFET structure with different device sizes, different trap sizes, and different trap positions. By comparing the variation of drain/source current with different parameters, the trend of drain / source current variation changing with each of parameters can be obtained: (1) The rate of drain current change is larger when device size is smaller; (2) There is a peak in the curve for the rate of drain current change, and when device size is scaled, the peak will become sharper and sharper; (3) When the devices with the same width, the curve slopes for the drain current change rate in the subthreshold region are also the same; (4) Drain/source current of trap at gate center of device is smaller than trap at gate edge; and (5) Drain/source current of trap near the source is smaller than trap near the drain. Second, after getting and analyzing the result, we assumed that in the same gate bias, the rate of drain current change would only relate to gate width ( ) instead of both gate width and gate length ( ) when it is in subthreshold region. Then, we verified the trap size in the TCAD simulation while determining the trap size in the model derivation; and vice versa. Based on the simulated result, we combined the two models into a new one using Boltzmann function so that there are two distinct characteristics, in subthreshold region and in strong inversion region. Then, it is a straight focused task to enable the application of the new model in the reproduction of experimental data.en_US
dc.language.isoen_USen_US
dc.subject隨機擾動電子訊號zh_TW
dc.subject缺陷zh_TW
dc.subjectRTSen_US
dc.subjecttrapen_US
dc.title高介電金屬閘金氧半場效電晶體之隨機擾動電子訊號:實驗、建模與TCAD模擬zh_TW
dc.titleHKMG MOSFET Random Telegraph Signals (RTS): Experiment, Modeling, and TCAD Simulationen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis


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