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dc.contributor.author蘇段凱en_US
dc.contributor.authorSu, Tuan-Kaien_US
dc.contributor.author林鴻志en_US
dc.contributor.author黃調元en_US
dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorHuang, Tiao-Yuanen_US
dc.date.accessioned2014-12-12T01:46:20Z-
dc.date.available2014-12-12T01:46:20Z-
dc.date.issued2011en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079811533en_US
dc.identifier.urihttp://hdl.handle.net/11536/46713-
dc.description.abstract在本論文中,我們藉由簡單的金氧半(MOS)電容結構,來研究高介電常數(high-κ)材料,包括二氧化鉿(HfO2)以及氧化鋁(Al2O3)的特性。我們改變沉積後高溫退火(post-deposition-annealing)的溫度,來研究其對高介電常數材料的影響。我們發現,對於氧化鋁來說,高溫退火可以使介電常數更高,並降低漏電流 ; 而對二氧化鉿來說,高溫退火亦可以使介電常數上昇,但同時也會使漏電流增加。這是因為在高溫的退火過程中,二氧化鉿會產生結晶的現象。我們也由量測出的數據,去萃取介面缺陷密度,而證實高溫退火可以使介面缺陷密度降低。此外,我們也量測二氧化鉿電容的遲滯現象(hysteresis),藉以觀察它捕捉電荷的能力。 我們也利用本實驗室最近發展出的多晶矽奈米線製程,來製作奈米線元件,此製程無須使用先進且昂貴的設備,其製作流程簡單且極富彈性。我們採用氧化鋁為阻擋氧化層以及二氧化鉿為電荷捕捉層,來製作TAHOS奈米線非揮發性記憶體元件。相對於以氮化矽為電子捕捉層的傳統元件,TAHOS元件展現出較佳的驅動電流以及次臨界擺幅(S.S),此外在寫入/抹除的效率上也有大幅的改善。 在可靠度方面,由於邊角效應(corner effect)的影響,使得大量的介面缺陷產生,因而在經歷忍耐度(endurance)測試後,次臨界擺幅及臨界電壓均會上升。而在電荷保持(retention)方面,預測在經過十年儲存期後,全部的元件均仍可維持0.5 V以上的記憶窗。zh_TW
dc.description.abstractIn this thesis, we have investigated the basic characteristics of two high-κ materials (i.e., HfO2 and Al2O3) with MOS capacitors. The effects of post-deposition-annealing (PDA) temperature on the properties of the dielectrics are studied. For Al2O3, a higher temperature tends to provide better film quality and higher permittivity. While for HfO2, a higher temperature also results in a higher permittivity, albeit the leakage current is also higher because of the film crystallization. The interface trap density is decreased after the PDA treatment. We also exploit the trapping capability of the HfO2 by studying the hysteresis characteristics of the C-V measurements. We have also employed a simple and flexible way that was recently developed by our group to fabricate the NW devices. With the adoption of high-κ materials, a gate-all-around NW TAHOS NVM device was implemented. As compared with the NW SONOS NVM device with the same physical thickness in the dielectric stack, the TAHOS device possesses higher drive current and superior SS owing to the much reduced equivalent oxide thickness. Moreover, NW TAHOS devices also show significantly improved P/E speed. For endurance test, the SS values of all splits of devices increase with increasing cycles because of the corner effect. The data retention measurements performed on these devices predict that the memory window can be larger than 0.5 V after 10 years at room temperature.en_US
dc.language.isoen_USen_US
dc.subject奈米線電晶體zh_TW
dc.subject環繞全閘極zh_TW
dc.subject電荷儲存能力zh_TW
dc.subject忍耐力zh_TW
dc.subjectnanowire FETen_US
dc.subjectgate-all-arounden_US
dc.subjectretentionen_US
dc.subjectenduranceen_US
dc.subjectTAHOSen_US
dc.title高介電常數材料的特性分析及其在多晶矽奈米線非揮發性記憶體之應用zh_TW
dc.titleA Study on the Characterization of High-κ Materials and their Applications to Poly-Si Nanowire Nonvolatile Memory Devicesen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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