高效能增強型砷化鎵金氧半場效電晶體元件

Abstract

在這篇論文中，我們首先研究以砷化鎵材料沉積氧化鋁介電層的電容其電性特徵。較差的介電層品質會造成頻率響應/頻率分散( frequency dispersion), 延滯現象( hysteresis ), 平帶偏移( flab band shift ), 和不預期的低介電常數 (dielectric constant )。根據電性上的結果，在做過矽甲烷鈍化的電容展現出不只低的頻率分散而且延滯現象也很小。我們相信做過矽甲烷鈍化的電容可以有效降低砷化鎵氧化物的形成。為了證實我們的推論，我們利用電導的方式去萃取介面缺陷密度的分佈。接著，我們量測原子層沉積氧化鋁介電層於矽甲烷表面鈍化之砷化鎵電容其可靠度，可以透過在不同應力條件下捕捉/釋放電荷清楚了解不同介面的可靠度。我們觀察到矽甲烷表面鈍化後 的砷化鎵電容其可靠度有明顯的提升。接下來，我們在砷化鎵的不同晶相上做電性研究，而發現在(111)A的表面晶相上電容特性獲得了改善。當外加一個更大的正電壓，能帶可以向下彎曲使表面的本質能階Ei低於費米能階EF。換句話說，砷化鎵能隙中間的介面缺陷值降低，使費米能階可以移動到接近傳導能階。我們認為是不同晶相的表面的結構產生的改善。 串聯電阻的大小是影響金氧半場效電晶體元件效能的重要因素，源極/集極的電阻將會抑制最大驅動電流。我們利用ＣＴＬＭ這種結構討論其串聯電阻包括片面電阻率(sheet resistivity )和接觸電阻率( contact resistivity )。根據這些電性特徵，我們發現片面電阻率在30keV&80keV的離子佈植能量比在50keV的離子佈植能量來的小，然而接觸電阻卻是相反。除此之外，由活化溫度的條件觀點來看，我們發現片面電阻率在850oC比在950oC活化溫度來的小，然而接觸電阻卻是相反。我們統整可以找到最理想的條件為50keV的離子佈植能量和活化溫度850oC。但接面二極體在950oC活化溫度和合金金屬400oC30s的條件下順向電流沒有明顯的被抑制。我們將片面電阻率、接觸電阻率和歐姆接觸的條件優化，最後利用這些條件在不同晶相上將金氧半場效電晶體元件成功製作出來並量測其特性。除此之外，我們也製作出砷化鎵嵌入鍺源極和集極的金氧半場效電晶體元件並探討其特性。

In this thesis, firstly, we have studied the electrical characteristics of GaAs capacitors with Al2O3 dielectric. Poor dielectric quality results in frequency dispersion, hysteresis, flab band shift, and unfavorable low dielectric constant. According to these electrical characteristics, the passivation sample displayed not only small frequency dispersion, but also small hysteresis. We believed that the surface treatment of SiH4 passivation can efficiently diminish the formation of GaAs native oxide, and improve the effect of Fermi-level pinning phenomenon. In order to confirm the speculation, we used the conductance method to extract distributions of Dit for different interface passivation. Next, we measured the reliability of silane surface passivated for gallium arsenide capacitors with atomic-layer-deposited Al2O3 gate dielectrics. A clear understanding of reliability of different interfaces, via charge trapping/detrapping studies under different stressing condition, we observed the silane passivation can improve the reliability of gallium arsenide capacitors. Then, we studied the electrical characteristics on GaAs MOS capacitor with the different surface orientation of substrates. The characteristics was improved on GaAs MOS capacitor with (111)A surface orientation. When a larger positive voltage is applied, the bands bend more downward so that the intrinsic level Ei at the surface crosses over the Fermi level EF. On the other hand, the velue of Dit in the middle of energy bandgap was reduced, so the EF of surface on GaAs could reach to near conduction level. We assumed that the improvement resulted from the different structure of surface on orientation. The series resistance is an importance factor for metal-oxide-semiconductor field effect transistors (MOSFET) device performance. The source/drain ( S/D ) resistance will suppress the maximum driving current. We discussed series resistance including sheet resistivity and contact resistivity by CTLM structure. According to electrical characteristics, we discovered that the sheet resistivity at 30keV&80keV is lower than 50keV implant energy. However, the contact resistivity is just contrary. In addition, from the point of temperature, we found that the sheet resistivity at 850℃ is lower than 950℃, and the contact resistivity is just contrary. We can conclude the optimized condition for GaAs ohmic contact that was implanted at 50keV and the activation temperature at 850℃. But, the junction of forward current was not suppressed significantly at activation temperature 950oC and alloy metal 400oC 30s. We optimized conditions of sheet resistivity, contact resistivity, and Ohmic RTA time. Finally, we used these conditions to fabricate metal-oxide-semiconductor field effect transistors with the different surface orientation successfully and measured electrical characteristics. In addition, we also fabricated GaAs MOSFET with embedded Ge source/drain and studied electrical characteristics.