二位元分離式閘極氮化矽快閃式記憶體之先進操作方法探討

Abstract

此論文將提出在二位元分離式閘極氧化矽快閃式記憶體上先進的操作方法。在許多種不同的分離式閘極結構，源極注入(SSI)最常被使用在寫入以及帶對帶電洞入射(BTBHHI)則是用於抹除。有鑒於常見入射電荷的操作方法下，電子與電洞在底層氧化層的反應將會導致些可靠度上的議題，還有，底層氧化層的應力感應漏電流(SILC)現象已經在快閃記憶體中被視為主要的可靠度議題。在不同的抹除方法中,熱電洞入射引起的氧化層退化已被發現是蠻嚴重的情形，論文裡我們將提出新的抹除操作模式來抑制抹除對氧化層的破壞。 首先關於新的操作模式的電壓時間關係使用了多循環脈衝系列來加強寫入/抹除的效率，在寫入方法中-順向偏壓促進電子入射(FBEI)是由順向偏壓促進電子入射以及新的抹除方法-順向偏壓促進熱電洞入射(FBHHI)則是藉由合適的順向偏壓來產生電洞，FBEI可以達成低電壓以及高速度的操作目的，而抹除時使用FBHHI可以比BTBHHI用更少的時間產生更多的電洞。從實驗結果可得知新的操作模式比常見的操作更可靠。 最後，我們利用特殊的分離式閘極結構來分析不同的寫入方式造成的電荷分佈以及第二位元的影響(SBE)，並且在二位元的操作上使用多循環脈衝系列的操作方式，我們可以得到相對於常見的操作較好的性能及可靠性表現。

In this thesis, a novel operating scheme has been proposed for 2-bit/cell split gate SONOS. For a certain design of split gate structure, source-side injection (SSI) is usually used for programming and band-to-band hot hole injection (BTBHHI) is used for erase. By using the conventional operating method of charge injection, the interaction between the generated electron and hole pairs could cause the reliability issue for bottom oxide. Stress induced leakage current (SILC) at the bottom oxide has been discussed as a major reliability issue in flash memory. Among different erase method, hot hole injection induced oxide degradation has been found to be most serious condition. In thesis, we propose the new operating scheme to suppress the oxide damage during erase.

First, the new timing diagram for novel operating scheme used the multi-cycle pulse series to enhance the efficient of Program/Erase. For the programming method, Forward bias assisted Electron Injection (FBEI), achieved by forward-bias assisted electron injection, the new erase method, Forward Bias assisted Hot Hole Injection (FBHHI), achieved by suitable forward-bias assisted hole generation were proposed. A lower voltage operation and high speed operation can then be implemented in FBEI program. For the erase, FBHHI can supply more holes and less time than BTBHHI in the same operation condition. The results showed that the new operation schemes are more reliable than conventional operation.

Finally, we used the specific split gate structure to analyze the charge profiling of various program methods and second bit effect (SBE). And then, a 2 bit/cell operation for split gate SONOS by using multi-cycle pulse series, in which better performance and reliability can be achieved in comparison to conventional operation scheme, e.g. SSI or BTBHHI etc.