标题: 应用于三维可程式逻辑闸阵列之热感知摆放与绕线演算法
Thermal-Aware Placement and Routing for 3D FPGAs
作者: 张瀚元
黄俊达
电子研究所
关键字: 热感知;三维可程式逻辑闸阵列;摆放;绕线;热模型;thermal-aware;3D FPGA;placement;routing;thermal model
公开日期: 2011
摘要: 新兴的三维技术被认为是获得更好的系统性能及更易于整合的解决方案,其堆叠多个晶粒(die)至单一晶片(chip)并利用直通矽穿孔(through-silicon vias, TSVs)做为垂直方向的连接。另一方面,可程式逻辑闸阵列(FPGAs)具有许多优点,是目前产品设计的主流选项之一。因此很自然的,三维可程式逻辑闸阵列(3D FPGAs)可以更进一步提升系统效能。然而,在三维整合技术里,较高的功率密度(power density)与较长的散热途径(heat dissipation path)使得散热问题较传统的二维积体电路严重。因此发展具备热感知(thermal-aware)的三维可程式逻辑闸阵列自动合成框架(framework)是相当重要的。针对这个目标,我们在这篇论文提出一系列适用于三维可程式逻辑闸阵列(3D FPGAs)的精准细微(fine-grained)热电阻模型以及称为TherWare的热感知摆放(placement)与绕线(routing)演算法。在摆放时,我们不仅依照逻辑方块(logic tile)之间的影响与每个方块位置的散热途径来分配对应的逻辑区块(Configurable Logic Block, CLB),还会设法抑制因过长导线所增加的连线功率(interconnect power);此外,在绕线阶段更将同时考虑总消耗功率最简化及功率分布之均匀度对于温度的影响。由实验结果可以证实,相较于现行已知的热感知合成框架,经由TherWare所产生的合成结果在只需要增加些许电路延迟与程式执行时间的情况之下,最佳化过后的系统其最高温、温度标准差及最大温度梯度都能够被大幅地改善。
The emerging 3D technology, which stacks multiple dies within a single chip and utilizes through-silicon vias (TSVs) as vertical connections, is considered a promising solution for achieving better performance and easy integration. Meanwhile, field programmable gate array (FPGA) is one of the mainstream design solutions with lots of advantages. Therefore, 3D FPGA is a natural extension for further performance optimization. However, in 3D integration technology, the thermal issue is exacerbated mainly due to larger power density and longer heat dissipation path. As a result, the thermal-aware framework has been getting lots of attention in electronic designs. For this purpose, we propose a set of precise fine-grained thermal resistive models and a thermal-aware backend (placement and routing) flow named TherWare dedicated to 3D FPGAs in this thesis. In the placement stage, we not only consider the power distribution of logic tiles and heat dissipation path for each tile but also prevent the increase of interconnect power due to longer wirelength. In the routing stage, both power minimization and power distribution are considered. Finally, the experimental results show that our proposed TherWare can significantly improve maximum temperature, temperature deviation and maximum temperature gradient only with a minor increase in delay and runtime compared with the prior arts.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079811632
http://hdl.handle.net/11536/46797
显示于类别:Thesis


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