標題: 動態脈衝波字組線寫入邊界量測與內建脈衝寬度量測電路之設計與實現
Design and Implementation of Dynamic Word Line Pulse Write Margin Measurement with Build-in Pulse Width Measurement Circuits
作者: 王紹丞
Wang, Shao-cheng
周世傑
Jou, Shyh-Jye
電子研究所
關鍵字: 記憶體;量測電路;監控系統;純數位輸出;SRAM;monitor;skitter;all-digital
公開日期: 2011
摘要: 現今的電子產品功能越來越多,電路的設計也越來越複雜,記憶體的使用率也隨之上升。然而,記憶體的速度往往控制著整個系統的操作速度,在眾多種類的記憶體中,靜態隨機存取記憶體有較高的存取速度,故其常於系統中做為儲存裝置或為快取記憶體。而在靜態隨機存取記憶體中,又以6T架構有著較緊密的面積及較快的存取速度,在過去的二十年以來,一直是靜態隨機存取記憶體的主流。不過隨著製程的演進,到了奈米等級之後,製程的變異使得6T靜態隨機存取記憶體的讀取與寫入能力受到很大的退化,甚至導致功能失常。何況在一些低電壓操作的狀態下,6T靜態隨機存取記憶體的穩定性又更低,變得更容易被外在因素影響。因此我們便由靜態雜訊邊界來衡量一個靜態隨機存取記憶體的穩定性,其中又細分為讀取靜態雜訊邊界和寫入靜態雜訊邊界。但是在靜態的狀況下,對於靜態隨機存取記憶體的寫入是較有利的,因此我們希望能模擬靜態隨機存取記憶體的正常操作來測量寫入邊界。 我們提出了一個測試電路來監測6T靜態隨機存取記憶體的變異,在以不更動記憶體陣列的前提下,透過外部電路進行動態寫入邊界的測量。為了能模擬靜態隨機存取記憶體的正常操作,使用了環型振蕩器產生脈衝,如此一來便能在字元線上產生與正常操作類似的脈衝波型。對於這個短暫脈衝,我們使用了歪斜與抖動的消除控制器,它本是為了消除兩個訊號間的歪斜及抖動,在此我們應用於量測波型,由於有著非常小的負載,我們可以在不影響到字元線的情況下,直接並精確(10ps)的量得字元線上的脈衝寬度,不再是依靠模擬的結果作猜測。此外,這個測試電路的輸入輸出訊號皆數位化,可以全自動測量,加上256k位元的測試陣列,我們可以快速的獲得大量資訊並加以分析。為了在測量上有更大的彈性,我們可以個別降低記憶體陣列的供應電壓或者是字元線驅動電壓,甚至是預充電電路的電壓。最後,我們將這些架構實現於一個256kb的SRAM測試電路上,製程為55奈米製程。
In the SRAM design, 6T structure has higher density and speed and have been the mainstream of SRAM for the past two decade. But as the process scaling down to nanometer, the process variation makes the readability and writ ability of 6T SRAM get degraded, or even cause function fail. Worst of all, at low-voltage operation status, stability of 6T SRAM becomes much lower than usual case and more vulnerable to external factors. Conventional, we weigh the stability of SRAM is measured by static noise margin (SNM), which can be divided into read SNM and write SNM. However, in static conditions, write operation is much easier for SRAM. Hence, it shave have transition operation of SRAM to measure the write margin. In this thesis, we propose a testing circuit to monitor the write margin variation of 6T SRAM without changing the SRAM cell array and measure the dynamic write margin through an external circuit. We use ring oscillator to generate the short pulse and use skitter structure to measure the pulse width on word-line directly. Skitter outputs all-digital signal with high resolution (10ps) so the error is very small. This monitor circuit can measure the write margin and read margin of 6T SRAM with dynamic word-line pulse. The supply voltage, word-line voltage and bit-line pre-charge voltage are adjustable individually. Finally, a 256kb SRAM with the proposed monitor structure is designed and implemented by using 55nm CMOS process.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079811640
http://hdl.handle.net/11536/46806
Appears in Collections:Thesis