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dc.contributor.author黃暉舜en_US
dc.contributor.authorHuang, Hui-Shunen_US
dc.contributor.author郭建男en_US
dc.contributor.authorKuo, Chien-Nanen_US
dc.date.accessioned2014-12-12T01:46:35Z-
dc.date.available2014-12-12T01:46:35Z-
dc.date.issued2011en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079811643en_US
dc.identifier.urihttp://hdl.handle.net/11536/46809-
dc.description.abstract本篇論文的主要目的在設計應用於無線感測網路之低功率射頻前端接收器與傳送器電路。此接收器與傳送器被實現於一顆聯電90奈米CMOS製程的晶片當中,整顆晶片的大小為1360μm×1210μm。所設計之接收器為一組操作在1.4-GHz的低功率射頻前端接收電路,其包含有一顆低雜訊放大器、I/Q降頻混頻器以及一顆用以將此前後兩級交流耦合之變壓器。設計以共源級放大器串疊架構來實現低雜訊放大器,適用於在低功率操作之下做高效率之訊號放大以及電壓對電流之轉換。並且,設計三端變壓器將單端訊號轉換成為雙端訊號,進一步地省去訊號轉換之功率消耗。最後,設計以雙平衡混頻器之架構來實現降頻混頻器,把訊號降頻後再輸出。論文中針對變壓器的架構以及其共振操作加以分析與設計,用以提供最大電流轉換增益。所設計之傳送器為一組操作在1.4-GHz的低功率射頻前端傳送電路,其包含有一顆升頻混頻器、一顆前級驅動器以及一顆功率放大器。設計以被動架構來實現升頻混頻器,用以省去升頻混頻器之功率消耗。並且,設計以反向器架構來實現前級驅動器,其適用於在低功率操作之下對訊號的電壓擺幅做高效率的驅動。最後,設計以A類放大器架構來實現功率放大器,用以完成高線性度的功率放大器。本論文將低雜訊放大器之輸入阻抗匹配的電感和功率放大器之輸出阻抗匹配的電感整合於晶片當中,進一步地在晶片上實現系統整合。此接收器與傳送器不只是針對低功率消耗還設計其符合無線遠距醫療服務Wireless Medical Telemetry Service (WMTS)的1.4-GHz頻帶的各項規格。zh_TW
dc.description.abstractThis thesis aims to design a low-power 1.4-GHz transceiver front-end circuit for wireless sensor network application. The whole transceiver is implemented on a single chip by using UMC 90-nm CMOS technology, and the chip size is only 1360μm×1210μm. The designed receiver contains a low noise amplifier, I/Q down-conversion mixers, and a transformer which conducts AC coupling between the LNA and the mixers. The LNA is realized in the common-source cascode architecture which has high gain efficiency even in low-power operation. The 3-terminal transformer transfers the single-end signal to the differential form without power consumption. The I/Q down-conversion mixers are in the double-balance structure which is favorable for the direct-conversion receivers. This thesis focuses on the analysis of the transformer resonance operation for realizing the maximal current gain. The designed transmitter is composed of an up-conversion mixer, a pre-amplifier, and a power amplifier. The up-conversion mixer is realized in the passive architecture on the purpose of saving power consumption. The inverter-based pre-amplifier has efficient voltage gain with consuming a little DC current. The PA is realized by a class-A amplifier under the linearity consideration. The two inductances in the LNA input matching and the PA output matching are both integrated on this chip in order to achieve the sub-system integration. This transceiver is designed to not only reduce the power consumption but also meet all specifications of the 1.4-GHz band in Wireless Medical Telemetry Service.en_US
dc.language.isoen_USen_US
dc.subject低功率zh_TW
dc.subject接收器與傳送器zh_TW
dc.subject無線感測網路zh_TW
dc.subjectlow poweren_US
dc.subjectRF transceiveren_US
dc.subjectwireless sensor networken_US
dc.title應用於無線感測網路之低功率1.4-GHz射頻前端接收器與傳送器電路設計zh_TW
dc.titleLow-Power 1.4-GHz Transceiver Front-End Circuit Design for Wireless Sensor Network Applicationen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis


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