使用相位偵測技術之可適性電纜等化器

Abstract

本論文提出兩個使用相位偵測技術之可適性電纜等化器，可運用於有線通訊系統中。此提出之相位偵測技術避免使用傳統等化器中之整流器，因為整流器電路易受偏移(offset)影響。在此提出之相位偵測技術中，信號之斜率資訊被轉換成相 位資訊，此技術類似於數位化控制，可靠度更佳，不易受製程、電壓、溫度變異 影響，同時，不受輸入振幅大小及不一樣輸入資料型態的影響。為了增加等化器 之頻寬，使用了負電容與電感串聯等技術。本論文提出了兩個可適性電纜等化器，皆採用了相位偵測技術。第一個可適性電纜等化器可達到10Gb/s的資料傳輸率，使用台積電0.13μm CMOS製程製造，最長能補償到 24 英吋的FR-4電路板通道，此通道在 5GHz 時衰減了 18dB。量測顯示此電路在1.5-V的電壓供應下消耗39mW之功率，誤碼率小於10^-13。第二個可適性電纜等化器可達到6Gb/s的資料傳輸率，使用台積電0.18μm CMOS製程製造，最長能補償到61英吋的FR-4電路板通道，此通道在3GHz衰減了21dB。量測顯示此電路在1.8-V的電壓供應下消耗了31mW之功率，誤碼率小於10^-13 。

The thesis presents two adaptive cable equalizers with novel time-domain approach called the phase detection technique for application in wireline communication. This detection mechanism avoids offset-sensitive rectifiers which normally exist in conventional equalizers. Edge-speed information is converted into phase information in this technique. The proposed detection mechanism is similar to digital control, which makes it more reliable and more immune to PVT variations; meanwhile, it has advantages of input swing and data pattern independent. In order to improve the bandwidth of equalizer filter, negative capacitance, inductive peaking and other skills are employed. Two chips are implemented in this thesis. Both of them adopt the phase detection technique. The first chip implements a 10Gb/s adaptive cable equalizer in TSMC 0.13μm CMOS technology. It can compensate a 24-inch channel on an FR-4 PCB, which has an 18dB loss at 5GHz. The power dissipation is 39mW excluding the output buffer from a 1.5-V supply voltage and the measured bit error rate is less than 10^-13. The second chip implements a 6Gb/s adaptive cable equalizer in TSMC 0.18μm CMOS technology. It can compensate a 61-inch channel on an FR-4 PCB, which has a 21dB channel loss at 3GHz. The power consumption is 31mW without the output buffer from a 1.8-V supply voltage and the measured bit error rate is less than 10^-13.