混合訊號積體電路製程單晶片加速度計與前端電路設計

Abstract

本文提出一個單晶片 CMOS MEMS 電容式加速度計與微瓦特前端電路。為了優化加速度計的雜訊-功耗性能以達最小範圍，本文採用了一個目標規格驅動之電路-微機電系統協同設計流程。這個共同電路-MEMS設計流程，包括CMOS MEMS加速度計的質量-彈簧-阻尼參數計算流程和優化功耗-雜訊的讀出電路。在模擬讀出電路設計中，本文提出的電路架構結合捷波穩定和相關雙重採樣的方式，用以抑制低頻雜訊和直流偏移補償。在RMS輸入參考雜訊電壓在100Hz頻率下為9.82 nV/√Hz，其功耗在100 kHz調波頻率下為 41□W。 CMOSMEMS加速度計的設計流程說明了如何透過計算質量-彈簧-阻尼參數來得到最小化加速度計面積。

A monolithic implemented with standard 0.18□m Mixed-Signal MEMS (MS MEMS) process capacitive accelerometer with micropower analog front-end circuit is presented in this thesis. In order to optimize noise-power performance of the accelerometer, a specification driven circuit-MEMS co-design flow is adopted. The concurrent circuit-MEMS design flow includes mass-spring-damping parameter calculation flow for MEMS accelerometers and optimized power-noise reduction flow for readout circuits. In analog readout circuit design, the proposed circuit architecture combines chopper stabilization and correlated double sampling to suppress low frequency noise and compensate DC offset. The RMS input referred noise voltage is 9.82 nV/√Hz under 100Hz. The power consumption is 41□W at 100 kHz modulation frequency. The integrated circuit and accelerometer design flow shows how to calculate mass-spring-damping parameter for minimized accelerometer area.