SiGe BiCMOS 5GHz射頻接收器前端電路

Abstract

在這篇論文研究中，我們首先會討論到積體電路製程的發展，SiGe BiCMOS發展的進況及這個製程和Si CMOS的不同處，並比較其電路特性的優缺點。接著會探討兩個實做的電路主題；第一個主題為操作在高頻5.25GHz的低雜訊放大器，電路完全未採用晶片外元件做為匹配的設計以便日後和其他電路整合，在2.5伏特的的電壓下有7.5mW的消耗功率，並有S118.3dB，功率增益為4.6dB，S2210.9dB及IIP3有3dBm，雜訊指數則為9.3dB。因為實測操作頻率往低頻移動，造成增益及雜訊的阻抗匹配點接有所變動，所以實測的電路特性並不如模擬預期，我們對這方面做了探討。第二個主題是5GHz的低功率共電流低雜訊放大器及降頻混頻器，將Gilbert Cell混頻器疊接在差動的低雜訊放大器之上以達到共用電流的目的，設計成射頻訊號為5GHz及中頻訊號為10megHz以方便量測，利用電路板量測，並已預估到電路板的打線等所產生的高頻寄生效應，有-1dB的轉換功率增益及-5dBm的IIP3，電路操作在2.5伏特的的電壓下有5mW的消耗功率，且此量測結果和模擬結果有稍為的差距，我們針對了輸入轉導值及輸出端阻抗做了探討。以上兩組晶片皆以台積電SiGe BiCMOS 0.35-μm 的製程實現並完成量測和模擬比較討論。

This thesis contents two works. First of all, we discuss the development of SiGe BiCMOS technology and the comparison between the SiGe and Si technologies. The first circuit, we implement a fully integrated 5.25GHz RF low noise amplifier, this circuit has a 8.3dB S11, a 4.6dB power gain, a 10.9dB S22 , a 3dBm IIP3 and a 9.3dB noise figure, under the 7.5mw power consumption with a 2.5 V supply voltage. Because the operating frequency shift to lower frequency, the gain and noise impedance matching point are changed, the measurement performance is not as good as simulation. Furthermore, we have completed a low-power concurrent low noise amplifier and down-converter. A Gilbert Cell is stacked on the top of differential LNA to achieve the re-use of DC current. We choose The RF signal is at 5GHz and IF signal is at 10megHz for measurement conveniently. The circuit is on-board testing and all the effect of parasitic and bonding wires is being taken account. The conversion gain is -1dB and IIP3 is -5dBm under the 5mw power consumption with a 2.5 V supply voltage. We would find out the difference reasons between simulation and measurement. These two IC have fabricated in a TSMC SiGe BiCMOS 0.35-μm technology. Moreover, the measurement and comparison with simulation had been done.