0.5V 低電壓類比前端電路應用於生醫訊號紀錄

Abstract

隨著現代醫學的發達，可攜帶的生醫訊號量測裝置的需求越來越大。我們希望病人可以攜帶輕巧的監控裝置並可長時間的監控。本研究提出一個0.5-V低電壓,可程式化的CMOS類比前端積體電路應用在生醫訊號測量。我們的設計能夠處理心電圖，肌電圖，以及腦波訊號，並且利用差動放大、chopper-stabilized與交流回授電路技巧阻隔電極片的直流偏移，共模雜訊，以及1/f雜訊。類比前端放大電路的input-referred noise floor為36 以及3.26的noise-efficient factor (NEF)。另外，可程式化放大器的電壓增益可以透過數位介面控制，實現上容易與DSP整合。總功率消耗是4.21μW (不包含偏壓電路)。所提出的電路架構將被實現在UMC CMOS 90 nm的製程，其晶片面積為0.75mm X 0.66mm (不包含PAD)

In this thesis, a 0.5-V low voltage programmable CMOS analog front-end IC for biomedical signal acquisition is presented. The design deals with Electrocardiogram (ECG), Electromyogram (EMG), and Electroencephalogram (EEG) signals, while reject DEO (Differential Electrode Offset), common-mode disturbance and solve flicker noise by differential circuits and chopper-stabilized technique with an AC feedback circuit. The analog front-end circuits achieve 36 input-referred noise floor and the noise-efficient factor (NEF) of 3.26. The programmable gain amplifier (PGA) sets voltage gain with digital interface, which could be integrated with DSP easily. The total power consumption is 4.21μW (biasing circuits are excluded). The chip is realized in UMC 1P9M 90nm CMOS process. The active die area is 0.75mm X 0.66mm.