標題: | 可調式頻寬/增益之四通道生理訊號擷取晶片設計 Tunable BW/Gain Circuit Design of Four-Channel Bio-Signal Acquisition |
作者: | 戴毓廷 林進燈 電控工程研究所 |
關鍵字: | 生理訊號;腦電圖;電流平衡式儀表放大器;切換式電容低通濾波器;可程式化增益放大器;Biomedical signal;electroencephalogram (EEG);current-balancing instrumentation amplifier (CBIA);switched-capacitor low-pass filter (SCLPF);programmable gain amplifier (PGA) |
公開日期: | 2007 |
摘要: | 在人體所有的生理訊號中,其訊號振幅皆非常微弱,亦容易被受測者本身、量測環境及設備等因素所影響,故本論文提出適用於各種電生理訊號擷取之晶片設計。除了一般著重的低功率、低雜訊之外,同時提高共模訊號拒斥比(CMRR)與電源漣波拒斥比(PSRR),並將整體多通道前端電路整合實現在單一晶片上,不需要任何外接元件,除了兼具成本與晶片面積效益,亦可降低因複雜的接線對生理訊號在量測時所造成的干擾,使後端處理及分析的訊號品質能夠更為精確。另外,在系統加入了數位控制介面,根據不同生理訊號的需求,利用數位訊號去控制選擇所要的訊號放大倍率與系統頻寬。
本論文所設計的生理訊號擷取晶片包含:電流平衡式儀表放大器(CBIA)、類比多工器、切換式電容低通濾波器(SCLPF)、非重疊時脈產生器(Non-Overlapping Clock Generator)及可程式增益放大器(PGA)等電路。整個電路設計使用TSMC 0.18μm CMOS 1P6M 製程技術來實現,而整體晶片面積為0.823×0.953 。由模擬結果顯示,在頻率150Hz下,可獲得CMRR 135dB、PSRR+ 105dB,和PSRR- 112dB的效能。在操作電壓 0.75V下,總消耗功率約112.68μA,平均每一通道消耗功率約28.17μA。 Due to properties of low-amplitude and non-stationary, most of biomedical signals are easily influenced by examined persons, measured environment, and electronic devices. A novel analog circuit design is proposed in this thesis, which is suitable for various biomedical signal acquisitions. In addition to the consideration of low power and low noise, the multi-channel analog front-end integrated circuit (AFEIC) is designed with high common-mode rejection ratio (CMRR) and high power supply ratio (PSRR). This circuit is realized into a single chip without any external component. It can not only reduce the number of outer components, but also enhance a better signal-to-noise ratio enormously. In addition, to select system gain and bandwidth corresponding to different amplitude and frequency of biomedical signals, the controllable digital interface was also designed and integrated into AFEIC. In this thesis, AFEIC design is composed of four current-balancing instrumentation amplifiers (CBIA), one analog multiplexer, one switched-capacitor low-pass filter (SCLPF), one non-overlapping clock generator, and one programmable gain amplifier (PGA). These circuits have been integrated into a single chip of the total area of 0.823×0.953mm2 by using TSMC 0.18μm COMS Mixed-Signal RF General purpose MiM Al 1P6M 1.8&3.3V process. For the simulation results, the proposed chip can achieve 135dB of CMRR, 105dB of PSRR+, and 112dB of PSRR- at 50Hz. The total power consumption is about 112.68□W under □0.75V supply, and the power consumption is about 28.17□W per channel. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT009412636 http://hdl.handle.net/11536/80759 |
顯示於類別: | 畢業論文 |