應用於可攜式生理訊號擷取系統之頻寬/增益可調式低雜訊前端電路設計

Abstract

在人體所有的生理訊號中，由於擷取到的訊號振幅非常微弱，也容易被受測者本身、量測環境及設備等因素所影響，故本論文提出適用於各種生理訊號擷取之晶片設計。除了一般著重的低功率、低雜訊之外，同時提高共模訊號拒斥比(CMRR)與電源漣波拒斥比(PSRR)，並將整體前端電路整合實現在單一晶片上，完全不需要任何外接元件，除了兼具成本與晶片面積效益，亦可降低因複雜的接線對生理訊號在量測時所造成的干擾，使後端作處理及分析的訊號品質能夠更為精確。另外，在系統加入了數位控制介面，根據不同生理訊號的需求，利用數位訊號去控制選擇所要的訊號放大倍率與系統頻寬。 本論文所設計的生理訊號擷取晶片包含：電流平衡式儀表放大器（CBIA） 及切換式電容濾波器（SCF）、非重疊時脈產生器（Non-Overlapping Clock Generator）及可程式增益放大器（PGA）等電路。整個電路設計使用TSMC 0.35μm CMOS 2P4M 製程技術來實現，而整體晶片面積為0.907*1.129 。由模擬結果顯示，在頻率50Hz下，可獲得CMRR 155dB、PSRR+ 131dB，和PSRR- 127dB的效能。在操作電壓 1.5V下，總消耗功率約142.4μA。

Due to low-amplitude and non-stationary properties, most of biomedical signals are easy to be influenced by examined persons, measured environment, and electronic devices. The objective of this thesis is to propose a novel analog circuit design, which is suitable for various biomedical signal acquisitions. In addition to the consideration of low power and low noise, the analog front-end integrated circuit (AFEIC) is presented with design of high common-mode rejection ratio (CMRR) and high power supply ripple rejection ratio (PSRR). This circuit was realized into a single chip without any external component. It can not only reduce the number of outer components, but also greatly enhance a better signal-to-noise ratio. In addition, to select system gain and bandwidth corresponding to different amplitude and frequency of biomedical signals, the digital controllable interface was also designed and integrated into AFEIC.

In this thesis, AFEIC design includes one current-balancing instrumentation amplifier (CBIA), one switching capacitance filter (SCF), one non-overlapping clock generator, and one programmable gain amplifier (PGA). These circuits have been integrated into a single chip of the total area of 0.907□1.129mm2 by using TSMC 0.35□m CMOS 2P4M standard process. For the simulation results, the proposed chip can achieve 155 dB of CMRR, 131 dB of PSRR+, and 127 dB of PSRR- at 50 Hz. The power consumption is about 142.4 □W under □1.5V supply.