AN EFFICIENT TIMING MODEL FOR CMOS COMBINATIONAL LOGIC GATES

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DC Field	Value	Language
dc.contributor.author	WU, CY	en_US
dc.contributor.author	HWANG, JS	en_US
dc.contributor.author	CHANG, C	en_US
dc.contributor.author	CHANG, CC	en_US
dc.date.accessioned	2014-12-08T15:06:15Z	-
dc.date.available	2014-12-08T15:06:15Z	-
dc.date.issued	1985	en_US
dc.identifier.issn	0278-0070	en_US
dc.identifier.uri	http://hdl.handle.net/11536/4823	-
dc.language.iso	en_US	en_US
dc.title	AN EFFICIENT TIMING MODEL FOR CMOS COMBINATIONAL LOGIC GATES	en_US
dc.type	Article	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS	en_US
dc.citation.volume	4	en_US
dc.citation.issue	4	en_US
dc.citation.spage	636	en_US
dc.citation.epage	650	en_US
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.identifier.wosnumber	WOS:A1985AUB1500033	-
dc.citation.woscount	16	-
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