軟體化鎖相迴路平台之演算法開發

Abstract

本篇論文提出了基於軟體化鎖相迴路平台上其追蹤演算法之開發。此平台利用CPU可程式化的能力，結合ADPLL的相關矽智財 (Silicon Intellectual Property, IP) 模組，為PLL提供更有彈性的軟體控制。本論文所提出的追蹤演算法以軟硬體協同設計的方式，參數化不同IP模組之設定數值。以降低追蹤演算法的複雜度來增加程式編譯完後硬體平台的執行效率並改善軟體化的鎖定速度。所有的矽智財以標準元件數位電路的方式實作於TSMC 65nm的製程上。

The thesis is proposed an algorithm in the software-defined phase-locked loop platform. The proposed SDPLL platform combines several silicon IPs including CPU and PLL modules. Furthermore, the platform uses the computing power and programmable capability of CPU to provide flexible software controllability for PLL. In the thesis, the proposed tracking algorithm can coordinated with different IPs from embedded system design. Moreover, the thesis improves the efficiency of PLL tracking algorithm by decreasing the complexity of algorithm and enhances the performance of the system platform. All IPs are implemented by standard-cell-based design in TSMC 65nm process.