完整後設資料紀錄
DC 欄位語言
dc.contributor.author郭瀚文en_US
dc.contributor.authorKuo, Han-Wenen_US
dc.contributor.author蔡淳仁en_US
dc.date.accessioned2014-12-12T01:52:26Z-
dc.date.available2014-12-12T01:52:26Z-
dc.date.issued2011en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079855614en_US
dc.identifier.urihttp://hdl.handle.net/11536/48351-
dc.description.abstractAbstract Java Runtime Environment (JRE) is becoming a popular application platform for complex multimedia embedded systems today. In this thesis, we present the architecture design of a reusable Java accelerator IP for application processors for embedded systems. The accelerator IP cooperate with a general purpose processor (GPP) core to support the JRE. The GPP core is responsible for running service routines to support Java tasks such as I/O requests, dynamic class loading, heap memory management, etc. The proposed Java accelerator IP is a double-issue Java core in charge of execution of the Java applications. More importantly, it is easy to integrate such Java accelerator IP into existing embedded systems both hardware-wise and software-wise. On the software side, it does not rely on any full-blown OS (such as Linux) running on the GPP. Only a thin kernel that maintains the execution of interrupt-driven Java service routines is necessary to support the JRE. On the hardware side, the communication between the Java accelerator IP and the GPP core is achieved using a memory sharing table and an interrupt-driven mailbox device. The proposed Java embedded platform with the Java accelerator IP has been implemented on the Xilinx Virtex-5 ML507 FPGA development board.zh_TW
dc.description.abstractAbstract Java Runtime Environment (JRE) is becoming a popular application platform for complex multimedia embedded systems today. In this thesis, we present the architecture design of a reusable Java accelerator IP for application processors for embedded systems. The accelerator IP cooperate with a general purpose processor (GPP) core to support the JRE. The GPP core is responsible for running service routines to support Java tasks such as I/O requests, dynamic class loading, heap memory management, etc. The proposed Java accelerator IP is a double-issue Java core in charge of execution of the Java applications. More importantly, it is easy to integrate such Java accelerator IP into existing embedded systems both hardware-wise and software-wise. On the software side, it does not rely on any full-blown OS (such as Linux) running on the GPP. Only a thin kernel that maintains the execution of interrupt-driven Java service routines is necessary to support the JRE. On the hardware side, the communication between the Java accelerator IP and the GPP core is achieved using a memory sharing table and an interrupt-driven mailbox device. The proposed Java embedded platform with the Java accelerator IP has been implemented on the Xilinx Virtex-5 ML507 FPGA development board.en_US
dc.language.isoen_USen_US
dc.subject系統晶片zh_TW
dc.subjectJava執行環境zh_TW
dc.subjectJava處理器zh_TW
dc.subjectJava加速器zh_TW
dc.subject動態類別載入zh_TW
dc.subject嵌入式系統zh_TW
dc.subjectSoCen_US
dc.subjectJREen_US
dc.subjectJava processoren_US
dc.subjectJava accelerator IPen_US
dc.subjectDynamic class loadingen_US
dc.subjectEmbedded systemen_US
dc.title嵌入式Java加速器系統設計zh_TW
dc.titleDesign of Java Accelerator IP for Embedded Systemsen_US
dc.typeThesisen_US
dc.contributor.department資訊科學與工程研究所zh_TW
顯示於類別:畢業論文


文件中的檔案:

  1. 561401.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。