完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 郭瀚文 | en_US |
dc.contributor.author | Kuo, Han-Wen | en_US |
dc.contributor.author | 蔡淳仁 | en_US |
dc.date.accessioned | 2014-12-12T01:52:26Z | - |
dc.date.available | 2014-12-12T01:52:26Z | - |
dc.date.issued | 2011 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT079855614 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/48351 | - |
dc.description.abstract | Abstract Java Runtime Environment (JRE) is becoming a popular application platform for complex multimedia embedded systems today. In this thesis, we present the architecture design of a reusable Java accelerator IP for application processors for embedded systems. The accelerator IP cooperate with a general purpose processor (GPP) core to support the JRE. The GPP core is responsible for running service routines to support Java tasks such as I/O requests, dynamic class loading, heap memory management, etc. The proposed Java accelerator IP is a double-issue Java core in charge of execution of the Java applications. More importantly, it is easy to integrate such Java accelerator IP into existing embedded systems both hardware-wise and software-wise. On the software side, it does not rely on any full-blown OS (such as Linux) running on the GPP. Only a thin kernel that maintains the execution of interrupt-driven Java service routines is necessary to support the JRE. On the hardware side, the communication between the Java accelerator IP and the GPP core is achieved using a memory sharing table and an interrupt-driven mailbox device. The proposed Java embedded platform with the Java accelerator IP has been implemented on the Xilinx Virtex-5 ML507 FPGA development board. | zh_TW |
dc.description.abstract | Abstract Java Runtime Environment (JRE) is becoming a popular application platform for complex multimedia embedded systems today. In this thesis, we present the architecture design of a reusable Java accelerator IP for application processors for embedded systems. The accelerator IP cooperate with a general purpose processor (GPP) core to support the JRE. The GPP core is responsible for running service routines to support Java tasks such as I/O requests, dynamic class loading, heap memory management, etc. The proposed Java accelerator IP is a double-issue Java core in charge of execution of the Java applications. More importantly, it is easy to integrate such Java accelerator IP into existing embedded systems both hardware-wise and software-wise. On the software side, it does not rely on any full-blown OS (such as Linux) running on the GPP. Only a thin kernel that maintains the execution of interrupt-driven Java service routines is necessary to support the JRE. On the hardware side, the communication between the Java accelerator IP and the GPP core is achieved using a memory sharing table and an interrupt-driven mailbox device. The proposed Java embedded platform with the Java accelerator IP has been implemented on the Xilinx Virtex-5 ML507 FPGA development board. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 系統晶片 | zh_TW |
dc.subject | Java執行環境 | zh_TW |
dc.subject | Java處理器 | zh_TW |
dc.subject | Java加速器 | zh_TW |
dc.subject | 動態類別載入 | zh_TW |
dc.subject | 嵌入式系統 | zh_TW |
dc.subject | SoC | en_US |
dc.subject | JRE | en_US |
dc.subject | Java processor | en_US |
dc.subject | Java accelerator IP | en_US |
dc.subject | Dynamic class loading | en_US |
dc.subject | Embedded system | en_US |
dc.title | 嵌入式Java加速器系統設計 | zh_TW |
dc.title | Design of Java Accelerator IP for Embedded Systems | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 資訊科學與工程研究所 | zh_TW |
顯示於類別: | 畢業論文 |