高速可變長度快速傅立葉轉換處理器伴隨混合格式訊號設計

Abstract

隨著無線通訊迅速的發展下所需的傳輸速度越來越快，於是正交分頻多工被提出以達到高頻寬使用率。在正交分頻多工技術裡面，快速複利葉轉換(FFT)是一個占很大量的計算以及硬體之區塊。因此本篇著重於如何去設計一個處理器，一方面可以達到高速規格需求，一方面則是可以減低他的硬體花費。首先所提出FFT處理器是一條單路徑的架構，它結合Radix-2及Radix-4演算法來完成512、1024、2048三種長度點數的處理。其中為了要強化他的訊號對量化雜訊比(SQNR)，我們採用了浮點數表示法讓資料可以更準確的表達，減低若是以固定點表示法所需要的硬體消耗。最後我們藉著管線化實作達到速度需求並完成此FFT處理器。

The requirement of access speed is more and more fast with the wireless communication is developed rapidly. Hence the OFDM is proposed to reach the high usage of bandwidth. In the OFDM technology, the FFT is a block which occupies the large calculation and area cost. Therefore this thesis emphasizes two points, one is high speed, and the other is low area cost. First, the proposed FFT processor is single path, and it combines Radix-2 and Radix-4 algorithms to process 512/1024/2048 length of points. In order to enhance the performance of the SQNR, we adopt the floating format to represent the signal and reduce the hardware cost with fixed format. Finally, we reach the speed standard with the pipelined implementation and complete the FFT processor.