標題: | 利用專利分析與成長曲線評估半導體奈米製程發展以HKMG, Strained Silicon, Nanolithography, TSV爲例 Patent Analysis and Logistic Growth Model for the Development of Semiconductor—HKMG, Strained Silicon, Nanolithography, TSV as Examples |
作者: | 周鴻揚 Chou, Hung-Yang Eric 袁建中 Yuan, J.C. Benjamin 管理學院科技管理學程 |
關鍵字: | 高介電金屬閘極;應變矽;奈米微影;矽穿孔;羅吉斯成長模型;費雪成長模型;專利分析;HKMG;Strained Silicon;Nanolithography;TSV;Logistic Growth Model;Fisher-Pry Growth Model;Patent Analysis |
公開日期: | 2010 |
摘要: | 半導體產業是一個新興而且是一個需要高度技術和創新的產業,並且是屬於知識經濟的範疇。知識經濟是指”以知識資源的擁有、配置、產生和使用,為最重要生產因素的經濟型態,其中,知識包括人類迄今為止創造的所有知識,以科學技術、管理和行為科學為最重要的部分。其具體形式則表現在人力資源和科技上.專利在知識經濟中扮演著重要的角色,而核心技術的專利指標與業的發展是密不可分的. 有著創新發展的專利是産業和企業再成長的重要關鍵因素。但隨着物理極限的到來,半導體製程技術是否可遵循過往的成長模式繼續發展下去便成為整體產業的重要關鍵因素。本研究即以量化半導體製程之核心技術專利並結合成長曲線來探討半導體產業是否能再次由新的技術創新和應用將產業從現階段再次延伸至新的成長期為研究標的。
本研究使用高介電金屬閘極、應變矽、奈米微影、矽穿孔等四種半導體奈米製程專利技術生命週期之觀點並結合羅吉斯及費雪成長模型,對半導體奈米製程技術發展進行趨勢的預測。獲得之主要結論有:第一、每一個新的半導體技術結點最終都受限於該相關的物理或化學極限,一旦突破某個界限之後,其效能的成長就變的非常的快速;而當其接近上限時,其效能的增進就變的非常的困難,成長也再度變得緩慢下來。第二、從羅吉斯成長模型和費雪成長模型的預測結論也可看出65nm到40nm的技術導成熟期預計為2005∼2008年間。與實際的量產和技術運用時間2008年和2009年初來看預測結果,此模型是有相當程度的準確性。因此半導體的特性是相當符合使用此模型來進行技術預測。
關鍵字 : 高介電金屬閘極、應變矽、奈米微影、矽穿孔、羅吉斯成長模型、費雪成長模型、專利分析 Semiconductor industry is classified as "knowledge economy" with characteristics of being technology-intensive and highly innovative. The knowledge economy refers to the use of knowledge technologies such as knowledge engineering and knowledge managementto produce economic benefits. Patents play significant parts in knowledge economy; patents that involves core technologies are critical drivers that move the progress of semiconductor industry. With semiconductor material reaching physical dilemma, question that whether semiconductor industry can still move ahead following past fast growth pattern is worthwhile to be revisited. This research analyses four key patents of semiconductor technology which are HKMG, Strained Silicon, Nanolithography and TSV, and combines these analysis along with Logistic Model and Fisher-Pry Model to forecast the future development of semiconductor industry. Based on the study, onclusions can be drawn as two main points. Point 1 is physical and material limitations will slow down the development of process node in semiconductor industry. However, growth pattern can then once again follow S curve with breakthrough of new material and process advancement. Point 2 is theoretical forecast that timeframe that advance node such as 65nm to 40nm technologies will be mature for use in mass production coincides with the timeframe that these technologies are actually applied in mass production. Therefore, the Logistic Model and Fisher-Pry Model are useful for technology forecast in semiconductor industry up to 40nm node.. Keywords: HKMG, Strained Silicon, Nanolithography, TSV, Logistic Growth Model, Fisher-Pry Growth Model, Patent Analysis |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079865515 http://hdl.handle.net/11536/48651 |
顯示於類別: | 畢業論文 |