溫度變化對覆晶錫銀銲錫接點之電遷移破壞模式研究

Abstract

「摩爾定律」是科技文明的奇蹟，它促使積體電路技術不斷的精進,電腦、智慧型手機…等個人行動裝置的普及,使人類的知識迅速爆增。1964年Intel 的共同創始人Gordon Moore 預言積體電路(Integrated Circuitry 或IC)上的電晶體( 電路開關)數目每年( 後修正為每18 個月)會增加一倍，為著名的「摩爾定律」(Moore’s Law)。現在電腦中央處理器(CPU)的晶片上已有數億個電晶體，而每個矽晶圓上會佈滿數百億個電晶體。這個數量遠超過世界的人口的總數。 隨積體電路的微縮化,覆晶銲錫具有高接腳密度､縮減封裝體積等優勢在電子產品走向輕、薄、短、小的趨勢中,成為進階元件的主流封裝型式。然而隨積體電路高電流､小尺寸的設計變化，覆晶銲錫接點內的電遷移現象成為元件可靠度的影響關鍵。在覆晶銲錫電遷移研究中，實驗發現電子流由導線進入銲錫時，因電子流流通面積劇變，造成電流集中效應,使銅金屬墊層溶解並消耗,導線與銲錫凸塊界面處常會有孔洞生成。研究發現，受電遷移影響,銲錫結構的破壞,主要分成兩種型態其一為Pancake-void ; 另一種型態為銅金屬墊層消耗溶解。然而形成這兩種破壞型態的主因,過去的文獻並沒有明確的定義這個部份。 在本文研究中，將利用凱文結構作為覆晶銲錫凸塊電性的量測，以高度50-μm、 Cu UBM 5-μm接合之銲錫凸塊的覆晶共晶錫銀銲錫，觀察覆晶銲錫結構在電遷移效應的影響,溫度的差異其所扮演的角色為何, 在高溫､低溫的環境下,覆晶銲錫結構的破壞機制又為何。同時觀察在不同電阻上升率下,討論覆晶銲錫結構所對應的破壞機制。

Moore's Law "is the miracle of the scientific and technological civilization, it makes popularly use of computers and become a part of public life. 1964, Intel founder Gordon Moore predicted that the number of transistors on integrated circuits will be doubled per year , that is the famous "Moore's Law". Hundreds of millions of transistors in a CPU chip, and each silicon wafer with tens of billions of transistors. This number is over than the total number of the world's population. In advanced electronic packaging because of its capability of higher I/O density and smaller package size. With higher current and smaller size trends, electromigration in flip-chip solder has become an critical of reliability concern. Flip-chip technology has become a mainstream trend From Flip chip solder electromigration study found that the electron current will be changed from the Cu trace into the solder joint, due to electronic current flow area cross-section difference , will lead to current crowding effect caused by current density inconsistent, the study found that affected by electro-migration, the the solder joint failure mode divided into two types, one is the Pancake-void; another type is UBM consume . However, the main cause of the formation of the two failure patterns, from past literature does not explicitly verify this part. In this study, we will using the Kevin structure to measure the resistance change of solder bumps in the electromigration effect and observe impact of the flip chip the solder joint under the electromigration effect , in the environment of high temperature and low temperature. the solder joint failure mechanism will be which type. While observing the rate of rise of the different resistance to discuss the solder joint failure degradation mechanisms .