適用於低密度奇偶校驗碼之改良式信度傳遞解碼法則及其硬體實踐

Abstract

由於低密度奇偶校驗碼 (low-density parity-check codes，LDPC Codes) 的錯誤更正能力接近向農 (Shannon) 極限，所以在近年來受到廣泛的討論且進而被使用在很多不同的通訊應用上。但在LDPC解碼演算法部分，低位元錯誤率及低複雜度往往無法兼得。 基於這個議題，在此研究中我們提出一個改良式演算法，希望在複雜度低於和積演算法情況下，錯誤更正能力依然保持甚至優於和積演算法。而此改良式演算法分別針對檢查點與位元點去做改善，在參考許多改良型最小和演算法及不同於傳統的位元點傳送訊息之方法，我們取其各優點並補強不足的地方，因而整合出此演算法。由模擬結果得知與原本的和積演算法比較，在白色高斯雜訊通道並使用雙相位鍵移調變之下，此演算法呈現最多有0.35dB的效能增進，特別是在短長度碼更有明顯的改善，且准循環低密度奇偶校驗碼和非准循環低密度奇偶校驗碼皆可被應用。最後，以WiMAX為例，將此改良之演算法實踐於FPGA板。

In recent years, low-density parity-check (LDPC) codes with iterative decoding have attracted a lot of attention owing to the remarkable performance near Shannon limit. Thus, LDPC codes have been well recognized as an excellent error correction coding scheme for many digital communication systems. However, about the design of LDPC decoders, it is di?cult to retain low bit error rate (BER) under reduced complexity. In this thesis, an improved decoding algorithm is proposed. We refer to several decoding algorithms improved from the min-sum algorithm and then advantages of these algorithms are integrated to achieve a better trade-o? between the complexity and BER performance. Revealed by the simulations results, our algorithm can even provide a signal to noise ratio gain about 0.35dB at most than the sum-product algorithm, especially for short length codes. Besides, it has good performance for both of quasi-cyclic low-density parity-check codes (QC-LDPC) and non QC-LDPC codes. Finally, this proposed algorithm for IEEE 802.16e application is implemented on an FPGA device.