以凱文結構研究厚銅金屬墊層覆晶銲錫接點在電遷移測試下不同階段的破壞模式

Abstract

隨著電子產品逐漸傾向輕、薄、短、小等趨勢，及具有更大效能的方向發展，3DIC電子構裝技術勢必成為未來的主流。而隨著尺寸變小，低焊錫高度的焊錫接點則是3DIC的一個重要關鍵。由於電遷移在低焊錫高度的行為尚未十分清楚，因此我們使用Sn2.3Ag，焊錫高度為15 μm的焊錫接點進行電遷移測試，觀察其破壞模式。為了精確的量測阻值的變化，我們使用了凱文結構，觀察不同阻值上升階段的破壞模式，其中包含阻值上升3%、5%、10%和20%不同階段，並使用電子顯微鏡來觀察微結構的變化，研究不同階段的破壞模式。其結果顯示，孔洞生成在介金屬化合物與金屬墊層之間，這與高bump height的破壞模式大不相同，因此本研究提供一個研究覆晶銲錫接點電遷移測試破壞機制的系統性方法。另外，因晶片內部不同材料的熱膨脹係數會導致應力產生甚至彎曲。我們使用了國家同步輻射中心的八環X光繞射儀研究矽晶片在電遷移測試後所造成的應變變化，分析破壞模式與內部應變的變化是否具有一定的關連。

As electronic products become smaller but have higher performance, three-dimensional integrate circuit（3DIC）has received more attention recently. Low bump height microbump is the key interconnection technology to build up the 3DIC. However, the electromigration（EM）behavior in the low bump height solder is still unclear. In this study, the Sn2.3Ag solder joint which bump height is 15 μm were used to observe the failure mode in the low bump height case. To precisely monitor the different stages of failure during accelerated EM testing, a specific Kelvin bump structure is designed and fabricated in these samples. While a 1.17 x 104 A/cm2 current density was applied at 150℃,the microstructures at different stages with the 3%、5%、10% and 20% resistance increase were obtained by scanning electron microscopy（SEM）. The resistance obtained by Kelvin bump structure showed three different stages, which differs from the results of traditional flip-chip solder joints. Voids formed in the interface of under-bump-metallization（UBM）and intermetallic compounds. With the proper designed Kelvin bump structure and well controlled test conditions, the different stages during EM test can be studied systematically. In this study, we also use x-ray diffraction in National Synchrotron Radiation Research Center`（NSRRC）to study the strain change of silicon die after different current stressing time, to find out the relationship between strain and failure mode.