三閘極金氧半場效電晶體利用基極偏壓調變臨界電壓

Abstract

本論文探討三閘極金氧半場效電晶體藉由基極偏壓調變臨界電壓的可行性。我們利用三維原子等級模擬探討隨機參雜濃度變動(Random Dopant Fluctuation)對於BULK三閘極元件中Punch-Through-Stopper (PTS)區域的影響。我們的研究發現藉由高濃度摻雜的PTS區域雖能有效的幫助基極偏壓調變元件的臨界電壓，但同時也造成額外Bulk三閘極電晶體的元件變異。因此，在比較BULK以及SOI三閘極元件的變異度時，上述效應的影響應該要納入考量。 由於bulk三閘極元件中PTS區域會引起額外的元件變異，因此利用基極電壓來調變SOI三閘極元件結構的臨界電壓似乎是個較佳的選項。為了有利於SOI三閘極元件多重臨界電壓的設計，我們準確地推導了具有高度深埋氧化層(BOX)厚度微縮性的次臨界解析模型。利用此模型，我們可以有效率且廣泛地探討SOI三閘極元件參數對於多重臨界電壓調變的影響。基於相同次臨界斜率(Subthreshold Slope)的比較基準之下，我們的研究指出低高寬比及薄深埋氧化層(BOX)的三閘極SOI元件結構設計可較有效率地利用基極偏壓來調變臨界電壓。

This thesis investigates the feasibility of threshold voltage (Vth) modulation through substrate bias for tri-gate MOSFETs. Through 3-D atomistic simulation, the random dopant fluctuations in the Punch-Through-Stopper (PTS) region of Bulk tri-gate devices are examined. Our study indicates that to achieve an efficient threshold-voltage modulation through substrate bias, the high-doping PTS region may introduce excess variation in Bulk tri-gate devices. This effect has to be considered when one-to-one comparisons between Bulk tri-gate and SOI tri-gate regarding device variability are made. Because of the PTS-induced variability in Bulk tri-gate, SOI tri-gate with substrate bias seems to be a better device structure to achieve multiple Vth. In order to facilitate multi-Vth device design in tri-gate SOI MOSFETs, we have derived an analytical subthreshold model with an accurate BOX-thickness scalability. Using this model, we can efficiently investigate multi-Vth device design in tri-gate SOI MOSFETs with wide range of design space. Under constant subthreshold swing criterion, our study indicates that tri-gate SOI device with low aspect ratio (AR) and thin BOX is a promising structure to enable efficient Vth modulation by substrate bias.