高壓製程之靜電放電防護設計

Abstract

隨著系統電源應用和管理裝置與IC產業的緊密結合，高壓金氧半場效應電晶體(HV MOSFET)已經廣泛運用在4C產品(電腦、消費性、通訊、和車用電子產品)，例如電源管理晶片、背光模組控制晶片、觸碰螢幕控制晶片與車用安全控制晶片等等。在高壓製程中，元件製作程序和相關製程參數較一般低壓製程來得複雜許多，使得元件製作和確保可靠度上更加困難，高壓元件的結構與傳統低壓元件相比，必須增加多道淡摻雜層及更為複雜的佈局法則，才能製作出高壓元件使其能操作在高於數十伏特或者更高的電壓。然而元件之靜電放電防護能力卻也因此受到製程程序和參數複雜的影響，使得寄生元件導通和排放靜電放電能量之能力下降。相比傳統低壓製程元件之下，高壓製程元件雖然能承受高操作電壓，但在靜電轟擊下卻難以有良好之靜電放電防護能力，但隨著市場需求量日與劇增且急需注意靜電放電防護可靠度之下，此情況開始受到高度重視，因此如何設計最佳化的高壓靜電放電防護元件，是本篇論文的探討重點。 在本篇論文中，靜電放電防護元件已被分別實現於162-nm 16-V double-diffused drain MOS (DDDMOS) 製程和0.25-μm 60-V bipolar CMOS DMOS (BCD) 製程，並分成三個主題探討量測結果，第一部分為探討傳輸線系統 (TLP system) 量測之脈衝密度 (pulse density) 的影響，由量測結果發現，傳統閘極驅動之靜電放電防護箝制電路 (gate-driven ESD clamp circuit) 由傳輸線系統量測之二次崩潰電流 (secondary breakdown current, It2) 與經由模擬人體放電模式 (human body model, HBM) 機台所測得之防護等級在等效耐受能力上有所差距，而其原因在本實驗中已被確認是由傳輸線系統之脈衝密度所造成，因此傳輸線系統之脈衝密度在量測高壓製程之靜電放電防護元件時，必須要慎重考慮。第二部分為探討高壓金氧半電晶體之安全操作範圍 (safe operating area, SOA)，為了節省佈局面積，會期望設計出具有良好靜電放電防護能力和寬廣之安全操作範圍之高壓金氧半電晶體。本部分即針對高壓金氧半電晶體元件結構進行調查，而實驗數據顯示，藉由適當調整高壓金氧半電晶體元件結構參數，在維持寬廣安全操作範圍下，能些微提升靜電放電防護耐受度。由於高壓金氧半電晶體之自我靜電放電防護能力提升有限，因此在第三部分提出靜電放電防護電路，用以保護內部電路之高壓元件。量測結果顯示，使用閘極驅動技術 (gate-driven technique)、自我基體觸發技術 (self-substrate-triggered technique) 之防護電路能具有良好之靜電放電防護耐受度。但由於其持有電壓 (holding voltage, Vhold) 低於工作電壓 (VCC)，將可能導致栓鎖效應 (latch-up) 的發生，為了避免栓鎖效應，後續可朝著提高單ㄧ高壓元件之持有電壓並採堆疊元件 (Stacked configuration) 的方式幫助提高防護電路之持有電壓。

Nowadays, the smart power technology has been developed and used to fabricate the display driver circuits, power switch, motor control systems, and so on. However, the process complexity and the reliability of high-voltage (HV) devices have become more challenging compared with the low-voltage (LV) devices. Among the various reliability specifications, on-chip electrostatic discharge (ESD) protection has been known as one of the important issues in HV integrated circuits (ICs). ESD is an inevitable event during fabrication, packaging and testing processes of integrated circuits. ESD protection design is therefore necessary to protect ICs from being damaged by ESD stress energies. In this thesis, the ESD protection circuits have been fabricated in 162-nm 16-V double diffused drain MOS (DDDMOS) process and 0.25-μm 60-V bipolar CMOS DMOS (BCD) process respectively. The experimental results and discussions are divided into three parts with different topics in ESD protection design. In part 1, the influence of pulse density in TLP measurement has been found. In the experimental results, the traditional gate-driven ESD clamp circuit has different secondary breakdown current levels (It2) when using different pulse density. Thus, in order to get a reasonable TLP It2 result, the pulse density should be taken into consideration, especially in HV processes. In part 2, the safe operating area (SOA) of HV MOSFET is studied. To minimize the layout area, it is preferable for HV MOSFET to have high ESD robustness and wide SOA simultaneously without any additional ESD protection circuits in HV ICs. In this work, the self-protected HV MOSFET is investigated with different device structures. According to the experimental results, the ESD robustness of HV MOSFET with modified device structure can be improved slightly under wide SOA. Therefore, to protect the internal HV devices against ESD stresses effectively, the extra ESD protection circuits should be additionally added outside the internal circuits. In part 3, the ESD protection circuits are proposed. Based on the experimental results, the proposed ESD protection circuits with gate-driven technique and self-substrate-triggered technique can have good ESD robustness. However, the holding voltage (Vhold) of the proposed ESD protection circuits is smaller than the power supply voltage (VCC). Such an ESD element used in the ESD protection circuit may be mistriggered to cause a latch-up failure. To overcome the latch-up issue, the stacked configuration and engineering the holding voltage of each ESD element will be a direction for further study.