由電路拓樸引導的降低漏電功耗之邏輯閘離散尺寸選擇架構

Abstract

邏輯閘尺寸選擇是電子設計自動化領域傳統問題。數十年來此問題已被廣泛地研究。然而，隨著現代積體電路設計對於高效能與低功耗的兼顧，過去的方法將遭遇新的挑戰。 在本論文中，我們藉由探討電路拓樸結構對於時序最佳化的影響來分析此問題。並提出了一種圖型表示法來表達鄰近電路結構的相互影響關係。應用此種表示法，我們提出了一個利用電路拓樸關係來解決邏輯閘尺寸選擇問題的架構。我們的實驗結果與2012 ISPD Discrete Gate Sizing Contest中前五名比較，平均排名為第三佳。

Gate sizing is a classic problem in the field of electronic design automation (EDA), and has been extensively studied for several decades. However, in the modern era, it is desired to have designs with both high performance and low power consumption. When dealing with modern industrial designs, prior academic approaches may face various new challenges. In this thesis, we analyze the problem by examining the impact of circuit topology in timing optimization, and propose a graph-based representation to analyze timing dependencies caused by circuit topological relationship. Through the application of segment dependency graph, we propose a gate sizing framework which exploits circuit topological relationship. Experiments conducted with the ISPD Contest 2012 benchmarks achieve the third best average ranking compared with the top five contestants in the ISPD 2012 Discrete Gate Sizing Contest.