標題: | A floating gate design for electrostatic discharge protection circuits |
作者: | Chou, Hung-Mu Lee, Jam-Wen Li, Yiming 電信工程研究所 友訊交大聯合研發中心 Institute of Communications Engineering D Link NCTU Joint Res Ctr |
關鍵字: | electrostatic discharge;robustness;floating gate;gate grounded;leakage current;negatively biased circuit;sub-100 nm CMOS device and circuit |
公開日期: | 1-二月-2007 |
摘要: | In this paper, a circuit design method for electrostatic discharge (ESD) protection is presented. It considers the gate floating state for ESD protection and negatively gate biased for leakage suppression under normal operations. The circuit is achieved by adding a switch device and a negatively biased circuit at the gate of ESD protection devices. Robustness and leakage of ESD protection circuit are improved. The circuit suits thin thickness of gate oxide of complementary metal oxide semiconductor (CMOS) devices due to an elimination of oxide damage. This approach benefits design of very large-scaled integration circuit and implementation of system-on-chip with sub-100 nm CMOS devices. (c) 2006 Elsevier B.V. All rights reserved. |
URI: | http://dx.doi.org/10.1016/j.vlsi.2006.02.005 http://hdl.handle.net/11536/11164 |
ISSN: | 0167-9260 |
DOI: | 10.1016/j.vlsi.2006.02.005 |
期刊: | INTEGRATION-THE VLSI JOURNAL |
Volume: | 40 |
Issue: | 2 |
起始頁: | 161 |
結束頁: | 166 |
顯示於類別: | 期刊論文 |