一個0.3V, 1GHz數位輔助式頻率合成器

Abstract

近年來, 採用無線能量擷取之可攜式電子裝置日漸普及。受限於系統功耗預算，次臨界電壓之電路設計技術日益受到重視。在系統晶片中， 時脈產生器為關鍵性組件。如何在次臨界電壓之設計下同時滿足高性能之需求，同時克服製程變異之障礙，為重要之設計挑戰 。

本論文提出一個可操作在高速(1 GHz)、低電壓(0.3V) 、同時克服製程與溫度變異之數位輔助式頻率合成器設計，其結合數位式頻率追蹤與類比式鎖相迴路概念，以提升低電壓操作時相位鎖定之精準度。此外，為了滿足未來高速資料傳輸所須之時脈頻率需求，其藉由相位合成之倍頻方法，大幅提升輸出頻率；在振盪器之設計上，採用預充式開關及位準提升的技巧，使得數位控制振盪器可在0.3 V 電壓之下操作，同時達到全擺幅、差動式輸出，在製程變異之條件下，其操作頻率可涵蓋 0.6 GH- 1.4GHz 之範圍, 功率消耗為 251μW, 模擬之相位雜訊在1MHz 時為-95dBc。

本設計晶片採用TSMC-90nm CMOS製程技術實現，晶片面積為0.86 x 0.85mm2。

Nowadays, portable electronic devices powered by wireless energy harvester are penetrating varieties of applications. As limited by the total power budget, circuit design techniques at subthreshold voltage level have drawn tremendous research efforts recently. In a typical SoC (system on a chip), clock generator plays the key role. It becomes a critical challenge to realize a clock generator operating at subthreshold voltage level while meeting the high performance specifications under process, voltage, and temperature variations. This thesis explores circuit techniques for high speed (1GHz) and low voltage (0.3 V) digital assisted frequency synthesizer design, which is capable of covering process and temperature variations. Combining with digital frequency tracking and analog phase locking techniques, it achieves high phase accuracy under subthreshold voltage level. To further comply with high speed serial link applications, a frequency doubler using phase combination technique is adopted. For the oscillator design, a pre-charged type bootstrapped delay stage is utilized. It delivers rail-to-rail, fully differential output swing under 0.3 V supply. The power dissipation is 251μW. Under process and temperature variations, it is capable of covering 0.6 GHz~ 1.4GHz. The simulated phase noise at 1 MHz is about -95dBc. The experimental prototype has been realized using TSMC 90 nm CMOS process. The chip size is 0.86 x 0.85mm2.