以漏電回授虛擬電阻元件應用於低雜訊前端放大神經電訊號晶片研究

Abstract

本論文旨在設計與實現一低雜訊及低功耗的前端放大電路研究，可應用於多種微弱的神經生理電訊號之放大，並結合積體電路技術來達到縮小系統體積、降低成本以及減少功率消耗，在此採用TSMC 0.35μm 2P4M CMOS標準製程，透過國家晶片系統設計中心進行晶片製作。在前端放大電路中使用虛擬電阻元件與電容構成一高通濾波器，並實現一個0.15Hz的低頻極點，用來濾除電極-皮膚間的直流偏移成分，避免造成放大器失真或飽和；同時本論文採用以漏電的方式來製作虛擬電阻元件，並與前端放大器結合，在1kHz時無寄生動態範圍具有58.1dB的線性度表現，接著，將所提出晶片與市售儀表放大器AD620進行相關係數比較，其數值大於0.93以上。最終，利用大鼠進行腦皮質電圖的量測與驗證，使用本論文所提之前端放大器可以符合神經生理訊號擷取之應用。

This thesis aims to design and implement a low noise, low power consumption front-end amplifier (FEA) that can be applied to various types of weak neural signal acquisition. It’s based on an integrated circuit technology to scale down system size and reduce cost and power consumption. As a case study, the proposed amplifier is designed and simulated using TSMC 0.35μm 2P4M CMOS standard process. The chip is fabricated through the National Chip Implementation Center. Using pseudo-resistor elements and capacitors to build a high-pass filter can achieve a low frequency pole at 0.15Hz. It can remove skin-electrode interface DC offset and avoid FEA saturation or distortion. Meanwhile, this thesis adopt leakage gate-controlled pseudo resistor and the FEA spurious free dynamic range about 58.1dB at 1 kHz. The proposed chip compared with commercially available instrumentation amplifier AD620 and then it’s correlation coefficient value is greater than 0.93. Finally, rat’s experiment results demonstrate the recording capability of the proposed FEA and it is suitable for neural signal recording applications.