Title: Investigation of inversion capacitance-voltage reconstruction for metal oxide semiconductor field effect transistors with leaky dielectrics using BSIM4/SPICE and intrinsic input resistance model
Authors: Lee, Wei
Su, Pin
Su, Ke-Wei
Chiang, Chung-Shi
Liu, Sally
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: MOSFET;MOS capacitance;C-V;ultrathin gate oxide and intrinsic input resistance
Issue Date: 1-Apr-2007
Abstract: This paper presents an inversion capacitance-voltage (C-V) reconstruction method for long-channel metal oxide semiconductor field effect transistors (MOSFETs) using the BSIM4/SPICE and the intrinsic input resistance (R-ii) model. The concept of Rii has been validated by segmented BSIM4/SPICE simulation. Since the Rii model is scalable with V-Gs and L, our R-ii approach is physically accurate. Due to its simplicity, this method may provide an option for regular process monitoring purposes.
URI: http://dx.doi.org/10.1143/JJAP.46.1870
http://hdl.handle.net/11536/4948
ISSN: 0021-4922
DOI: 10.1143/JJAP.46.1870
Journal: JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS
Volume: 46
Issue: 4B
Begin Page: 1870
End Page: 1873
Appears in Collections:Conferences Paper


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