數位訊號處理器中位址產生單元之位址位移配置最佳化

Abstract

近年來，嵌入式系統由嵌入式處理器、程式唯讀記憶體、隨機存取記憶體和特殊應用硬體組成單一電路的設計方式，在數位訊息處理的應用領域中逐漸增加。為了達到減少系統發展的花費以及上市的時間，在這類系統下開發程式的方式，也由組合語言轉變成使用高階的程式語言，如C、C++和Java。在本研究論文中，我們針對有限制的記憶體和具備位址產生器(AGUs)的嵌入式數位訊息處理器提出程式碼的最佳化技術。位址產生器提供間接定址模式(indirect addressing mode)，包括自動遞增(auto-increment)、自動遞減(auto-decrement)以及自動修改(auto-modify)的動作，而有別於之前的研究重點僅在自動遞增和自動遞減的動作，我們提出2個方法：Pruning method和基因演算法(Genetic Algorithm)，藉由同時利用上述的間接定址模式優勢，來減少位址計算所需的程式碼。我們的方法找出一組變數出在記憶體中的位址配置，使得需要用來明確計算變數位址的指令達到最少。根據實驗顯示，我們的方法較之前的研究，能更進一步改善12%到18%的位址計算指令程式碼。

In recent years, embedded systems consist of embedded processor, program ROM, RAM and any application-specific hardware on a single circuit are becoming increasingly in application domains such as digital signal processing (DSP). In order to decrease development costs and time-to-market, programming manner on such systems is changed from assembly language to high-level languages such as C, C++ and Java. In this paper, we present code optimization techniques for embedded DSP processors which have limited on-chip ROM and address generation units (AGUs). AGUs provide indirect addressing modes with auto-increment, auto-decrement and auto-modify operations. We present two approaches：Pruning method and Genetic Algorithm that reduce address arithmetic code size by taking advantage of these addressing modes simultaneously while previous works only focus on auto-increment and auto-decrement operations. Our approaches find an address offset assignment for variables in RAM such that explicit instructions for address arithmetic are minimized. Experiment results show improvements of 12% to 18% over the previous works in address arithmetic code size.