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dc.contributor.author周哲賢en_US
dc.contributor.authorChou, Che-Hsienen_US
dc.contributor.author蔡淳仁en_US
dc.date.accessioned2014-12-12T01:59:21Z-
dc.date.available2014-12-12T01:59:21Z-
dc.date.issued2011en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079955587en_US
dc.identifier.urihttp://hdl.handle.net/11536/50495-
dc.description.abstract本論文主旨在於多核心平台上使用software pipeline方法對H.264解碼進行加速。然而在多核心平台上使用software pipeline會有許多overhead 容易導致效能降低,Stage之間如何溝通、buffer的搬運、Hazards的問題和切割Stage的方法等都會造成很高的overhead。本論文使用Circual buffer 和 DMA…等方法降低software pipeline產生的overhead。我們利用PAC Duo平台實作並驗證我們提出的架構。受限於平台的核心數目,我們設計了two-stage的software pipeline。實驗結果software pipeline方法比沒使用software pipeline的效率平均提昇為1.8倍。zh_TW
dc.description.abstractIn this thesis, we present a software pipeline architecture to enhance performance of H.264 decoder on multiprocessor platform. However, performance of multiprocessor platform will be decreased easily due to the overhead of the software pipeline architecture such as communication between successive stage, buffer transfer, problem of Hazard, and computational load balance of the stages. This paper provides a method to reduce the overhead of the software pipeline architecture by using a circual buffer and a DMA. The design has been implemented and verified on a PAC Duo platform. Due to the constraint on the number of DSP cores on the target platform, a two-stage software pipeline is used to implement H.264. As a result, the performance of the two-stage software pipeline architecture is 1.8 times higher on average comparing to conventional implementations.en_US
dc.language.isozh_TWen_US
dc.subjectH.264zh_TW
dc.subjectPACen_US
dc.subjectSoftware Pipelineen_US
dc.subjectH.264en_US
dc.title在PAC平台利用軟體線程加速H.264視訊解碼zh_TW
dc.titleSoftware Pipeline Design for H.264 Decoding on a PAC Platformen_US
dc.typeThesisen_US
dc.contributor.department資訊科學與工程研究所zh_TW
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