支援可重組視訊編碼運作模式之系統單晶片架構設計

Abstract

在MMES LAB先前的研究中，提出了一個支援可重組視訊編碼運作模式的系統單晶片架構，並且實作在ARM Integrator的開發環境上。之前的系統架構因為受到ARM Integrator架構的限制，有很高的軟硬體溝通成本，此外，用以驗證此系統架構的H.264影像解碼器只支援intra模式的運作。此篇論文移植並且改良先前的系統架構到一個更有彈性的開發平台上，並且增加H.264影像解碼器對inter模式的支援。

This thesis presents a flexible SoC architecture for video decoding applications. Comparing to traditional hardwired codec approaches, the proposed framework is more flexible in the sense that it allows runtime construction of a new data path using available hardware and software functional units. This framework was original developed to support MPEG reconfigurable video coding (RVC) framework. However, there are some weaknesses in previous proposal. First, the original proposal was implemented on an SoC emulation platform (ARM Integrator) that has high software-hardware communication overhead. Secondly, the original design has not been verified with inter-frame decoding behavior. In this thesis, the complete system behavior of an H.264/AVC baseline video decoder has been implemented on a single-chip hardware-software co-implementation platform targeted for a large capacity FPGA. In particular, we have verified that the system behaviors of managing inter-frame can also be supported by the proposed flexible SoC architecture for RVC. In summary, the proposed SoC architecture is promising for practical applications.