調適提前讀取技術與重疊延遲排程之三維寬頻記憶體

Abstract

隨著記憶體與中央處理器存取速度的差距，記憶體已經成為系統效能的瓶頸，提升記憶體存取速度將有助於改善系統效能，由於近來TSV技術的成熟，晶片將可以用堆疊的方式來減少存取延遲時間。然而當系統晶片整合朝向三維發展，設計將會更複雜且效能更難被評估。 本篇研究我們實作一個三維記憶體模擬平台並且支援JEDEC寬頻記憶體傳輸介面來評估系統效能。 同時模擬器支援多執行緒平行處理來加快模擬時間。藉由分析寬頻記憶體的特性，我們提出了兩個機制來提升三維架構下的記憶體效能，調適提前讀取技術藉由分析記憶體區塊的存取密集程度及狀態並且參考指令列隊的數量來進行提前讀取，並且提高堆疊層間的平行度。重疊延遲排程則是利用TSV 傳輸延遲來提前執行充電指令，達到重疊延遲時間。

Due to the gap between memory and CPU speed, memory has become a bottleneck in computing systems. Improving memory access latency will improve system performance. As TSV technology matures, chips stacked in different stratums can reduce access latency. However, as SoC development moves towards 3D, it becomes increasingly difficult to evaluate complex systems designs. In this thesis an ESL platform is implemented which can support JEDEC wide I/O interface to evaluate memory performance. The simulator supports multi-threaded modeling and speedups the simulation time. After analyzing address mapping methods and properties of wide I/O, this thesis proposes two mechanisms to improve the performance of 3D architecture. Adaptive-prefetching will analyze memory intensive blocks and reference command queue status to prefetch data and improve RLP. Latency overlapping scheduling executes precharge command by beforehand analyzing TSV bus utilizaion.