標題: | 應用於多輸入多輸出正交分頻多工系統下射頻系統整合平台設計及低功耗之動態電流調整設計 The Design of Integrated Platform with RF for MIMO-OFDM Systems and Dynamic Current Scaling for Low-power Design |
作者: | 張致榮 Chang, Chih-Rong 陳穎平 Chen, Yin-Ping 資訊科學與工程研究所 |
關鍵字: | 多輸入多輸出;正交分頻多工;數位通訊驗證平台整合;動態電流調整;低功耗電路設計;MIMO;OFDM;FPGA;DAC;ADC;USB;USB GUI;RF;Low-power desigm;Dynamic Current Scaling |
公開日期: | 2012 |
摘要: | 多輸入多輸出(MIMO)的技術,近年來被廣泛運用於各通訊系統中。主要的原因在於可提供資料傳輸時的效率與品質。正交分頻多工(OFDM)的技術,由於可提供高速資料的傳輸,以及適合操作在多重路徑所引起之頻率選擇性通道,在無線通訊領域中,亦佔有舉足輕重的地位。因此結合此兩種技術,在新一代無線通訊系統中,MIMO-OFDM已經成為極具關鍵的技術。
在線通訊系統開發中,有幾個重要的議題,包括演算法的驗證平台的開發。以及通訊演算法晶片實作時,考慮功率消耗的低功耗電路設計。
MIMO-OFDM的通道非理想效應會影響傳輸品質,因此需要開發演算法去解決這些非理想效應問題。然而只開發演算法而沒有硬體去驗證演算法是不夠有價值的,本篇論文的重點就在於自行研發一套FPGA數位通訊驗證平台,其中整合DAC、ADC、USB與RF等硬體模組,搭配軟體所建構的圖形化界面與MATLAB通訊演算法開發,將4x4的MIMO-OFDM傳輸系統作實現,建立一套完整的無線通訊系統開發的驗證平台。運用此驗證開發平台,使得演算法設計更能真實的分析與評估其效能,且能快速的做驗證。藉由FPGA和RF模組,將理論值和實際測試的測量值相比較並且分析,提升演算法的價值與說服力,並加快演算法開發的效率。
除了驗證平台開發外,考慮到演算法的硬體實作時,功率的消耗將是重要的考量議題。因此本論文的另一部分是提出一個利用動態電流調整(Dynamic Current Scaling)的方式來節省功率上的消耗,將動態電流調整設計實作在快速傅立葉轉換器上,功率消耗省去40%。 In recent years, multiple-input multiple-output (MIMO) technology has been used widely in various communication systems. The main reason is that it can provide the efficiency and quality of data transmission. In addition, the orthogonal-frequency division multiplexing (OFDM) technology provides high-speed data transmission, as well as for operating in multipath over frequency selective fading channels, which has been adopted by many transmission systems. Therefore, the combination of these two technologies in next-generation wireless communication systems, MIMO-OFDM has become one of the most crucial technologies. There are some topics in wireless communication development. First issue is algorithm verification platform development. Second issue is application-specific integrated circuit (ASIC) implementation for low-power design. MIMO-OFDM system is very sensitive to the non-ideal front-end effects so need develop algorithms to solve them. However, only the development of algorithms without hardware to verify the algorithm is not valuable enough. In thesis we integrated a set of self-developed algorithm verification platform. This experimental platform integrated with field programmable gate array (FPGA), digital-to-analog converters (DAC), analog-to-digital converters (ADC), universal serial bus (USB) and radio frequency (RF) hardware module, combined with software graphical user interface (GUI), USB firmware, and comprises of MATLAB algorithms for solving non-ideal channel effects. The 4x4 MIMO-OFDM wireless communication system platforms are realized by combined with software and hardware co-design. Using this prototype platform makes the developed algorithms can accurate analysis and evaluate performance and verification. On the other hand, power consumption is more and more important issue on ASIC implementation. Another part of thesis we propose a dynamic current scaling (DCS) mechanism to achieve low-power design. For example the DCS mechanism is applied to fast Fourier transform (FFT) processor to achieve the 40% power saving. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079955604 http://hdl.handle.net/11536/50511 |
顯示於類別: | 畢業論文 |