标题: | 影像式红外线侦检像素缩小化制程开发 Development of Small Pixel Infrared Detectors for Mid-Wavelength IR Imaging Applications |
作者: | 罗俊杰 Jiunn-Jye Luo 张国明 Dr. Kow-Ming Chang 电子研究所 |
关键字: | 焦面阵列;红外线侦检器;披覆膜;漏电流;p+n二极体;平台蚀刻;铍离子植入;影像像素;p+n接面;Focal plane array;infrared detectors;passivation;leakage current;p+n diode;mesa etching;Be+ implantation;image pixel;p+n junction |
公开日期: | 2005 |
摘要: | 针对未来中波长3至5微米红外线影像感测应用上高解析度、高像素的要求,本论文研究如何将锑化铟二极体元件尺寸缩小化之相关制程技术,如p+n二极体表面批覆技术、隔离元件之平台蚀刻技术、及以离子植入法制作小尺寸二极体元件技术等。 为了达到提高影像解析度及增加像素之目标,位于光学系统焦面上,以二维分布之阵列型感测元件之像素单元尺寸大小势将朝缩小化方向发展;本篇论文利用一种由阳极氧化法及低温光化学气相沉积法所组合之双层薄膜作为披覆层,以控制锑化铟p+n二极体元件接面周边N传导型表面处于弱反相区,避免一般采用具有正电荷分布之单一CVD氧化层因感应表面电位为累积区而形成p+n+ 增强电场及增加漏电流的问题;这种堆叠而成之披覆层对锑化铟二极体元件表面电位效应,使得元件暗电流被控制在一个相对较低且稳定的工作区域,二极体元件将不需要额外闸控结构设计,此种堆叠而成之披覆层优点不仅在大幅降低制程复杂性,更因结构之简化而得以缩减像素单元尺寸大小。 为了缩小像素单元尺寸大小,对于隔离二维影像感测元件之平台蚀刻制程所导致元件结构均匀性问题,本论文研究柠檬酸/双氧水混合溶液对锑化铟的蚀刻机制,发现其与传统乳硝酸溶液不同;表面反应主控机制所产生隔离平台具有均匀性高、四边及角结构对称、侧壁斜度较大、及高度易于控制等特点,对于后续表面披覆层及金属镀膜在平台阶梯区域之覆盖度有很大改善。电性上吾人以线型阵列元件测试结构,针对整片晶圆进行暗电流分布测试,验证以柠檬酸/双氧水混合溶液制备元件之暗电流分布具有较佳之均匀性,此结果证明了以柠檬酸/双氧水混合溶液产生之平台结构较符合未来高密度阵列发展之需求。 为了达到缩小像素单元尺寸大小目的,除了结构要简化,制程本身亦需简化,以离子植入技术在锑化铟晶圆上形成接面制作二极体,由于精确的杂质浓度及植入深度控制,具有均匀性高及易于进行平面化制程等优点,因此对于缩小像素单元尺寸大小、增大像素密度,较传统的固态扩散技术将更有优势。然而离子植入造成的损伤及表面披覆技术的限制,使得以离子植入技术制作之p-n二极体在元件尺寸缩小化时,有元件性能退化及需要使用闸控结构调制元件表面电位之问题;本研究首次以两种不同介电薄膜堆叠组成之绝缘结构层作为铍离子植入锑化铟接面二极体之表面披覆层,并以实验验证元件接面面积小至20×20 μm2 之R0A已达到7.6 ×104Ω-cm2;根据实验数据及电路模型,吾人预估在元件接面面积小至15×15 μm2 之R0A仍可达到5 ×104 Ω-cm2水准。 This thesis studies the scale-down process issues of InSb photodiodes to meet the high resolution and high format requirements of next generation medium-wavelength infrared image sensing applications. It includes the passivation of the p+n junction surface on InSb, the mesa etching process to create isolated sensing pixels, and the fabrication of scale-down p+n diodes by Beryllium ion implantation. To achieve the goals of high resolution and high format in infrared imaging, the sensing pixels of the image array located on the focal plane of an image system will have to scale down to smaller size. In this study, a composite dielectric structure of anodic oxide and Photo-CVD oxide is used as the passivation layer on InSb diodes. The n-type surface at the junction peripheral will become depletion or weak inverted. By comparing with the characteristics of Photo-CVD oxide, the composite dielectric structure can help to get rid of the possibility of forming p+n+ regions, which may result in high electric field and high leakage current. The relatively low dark current of the InSb diodes passivated by the composite structure exclude the necessity of extra control-gate structure. This will help to simplify the fabrication processing; it will also help to reduce the dimension of the sensing pixel. The mesa structures, isolated p+n junctions, formed by lactic acid/nitric acid traditionally will have challenging issue on its uniformity performance if the pixel size is scale-down. This study found that the etching mechanism of citric acid/peroxide is surface reaction-limited dominant. The advantages including mesa height uniformity, symmetry edges and corners in the etched mesa square, slope side-wall, and more controllable on the mesa height have proved its superior performance on the step coverage for the succeeding coating of dielectric or metal film. Electrically, we evaluate the distribution of dark current of test structure distributed on the wafer. These results indicate that citric acid/peroxide solution can get better performance in uniformity. It is then more suitable for the applications of next generation high density array To reduce the pixel size, the fabrication processes should be simplified in addition to the simplification of device structure. Due to the embedded advantages of accurate dopant and junction depth control in the implantation technology, the InSb p+n diodes in the array will get higher uniformity and easier implementation to planar device structure. These advantages will help to reduce the pixel size, and increase the density of pixel in the image array. However, a gate-controlled structure is generally required to modulate the surface potential to get optimum device performance due to the damages and passivation issues. In this thesis, a composite dielectric film was used as the passivation layer. Without using the gate-control structure, we experimentally get R0A = 7.6 ×104Ω-cm2 for p+n diode with 20×20 μm2. Based on this result and circuit model, we expect the R0A will be 5 ×104 Ω-cm2 as the junction area is scaled down to 15×15 μm2. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT008511808 http://hdl.handle.net/11536/51223 |
显示于类别: | Thesis |
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