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dc.contributor.authorChang, TSen_US
dc.contributor.authorJen, CWen_US
dc.date.accessioned2014-12-08T15:01:44Z-
dc.date.available2014-12-08T15:01:44Z-
dc.date.issued1997-06-01en_US
dc.identifier.issn1350-2409en_US
dc.identifier.urihttp://hdl.handle.net/11536/520-
dc.description.abstractTwo embedded memory designs are proposed for video-signal processing. Concurrent line access performs multiple-port memory accesses at the hardware cost and access time of a single port. It uses 62.24% of the area required by a conventional dual-port memory and is only 7.6% larger than a single-port 2K x 8 memory. The block-access mode combines address decoders and generators, yielding block-access mode times 26% faster than conventional schemes for a 256 words x 32 bits memory size. Despite some preferred-access-order restrictions, the designs incur no loss of generality because video algorithms possess high data parallelism and low dependence.en_US
dc.language.isoen_USen_US
dc.subjectvideo-signal processingen_US
dc.subjecton-chip memory designsen_US
dc.titleOn-chip memory module designs for video-signal processingen_US
dc.typeArticleen_US
dc.identifier.journalIEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMSen_US
dc.citation.volume144en_US
dc.citation.issue3en_US
dc.citation.spage138en_US
dc.citation.epage144en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
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