| 標題: | 迴圈並行運算之計算模式與架構設計 COMPUTATIONAL MODELING AND ARCHITECTURE DESIGN FOR ITERATION-LEVEL PARALLEL COMPUTING |
| 作者: | 張志吉 陳稔 資訊科學與工程研究所 |
| 公開日期: | 1986 |
| URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT754241004 http://hdl.handle.net/11536/53158 |
| Appears in Collections: | Thesis |
- A Verification-Aware Design Methodology for Thread Pipelining Parallelization / Jian, Guo-An;Chien, Cheng-An;Chen, Peng-Sheng;Guo, Jiun-In
- Two design patterns for data-parallel computation based on master-slave model / Huang, KC;Wang, FJ;Tsai, JH
- Modeling of design iterations through simulation / Wang, Wei-Chih;Liu, Jang-Jeng;Liao, Tzong-Shiun
- Two systolic architectures for modular multiplication / Tsai, WC;Shung, CB;Wang, SJ
- BENCHMARKING AND ANALYSIS OF SUPERSCALAR ARCHITECTURE / SHIAU, YH;CHUNG, CP
- BENCHMARKING AND ANALYSIS OF SUPERSCALAR ARCHITECTURE / SHIAU, YH;CHUNG, CP
- A FLEXIBLE PARALLEL ARCHITECTURE FOR RELAXATION LABELING ALGORITHMS / LIN, SY;CHEN, Z
- DESIGN OF AN EFFICIENT DATA-DRIVEN PIPELINED COMPUTER ARCHITECTURE / LIN, CZ;TSENG, CC;CHI, KH
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