電流比值邏輯

Abstract

本論文提出一種新的邏輯結構，它是用二極體來取代傳統電流模式邏輯(Current Mode Logic)的負載電阻，使其工作於電流比值的邏輯位準上。此不同於傳統的電壓位準，故名電流比值邏輯(Current Ratio Logic)。 在本論文中，說明了電流比值邏輯的基本原理，並且使用SPICE程式，模擬比較電流比值邏輯與電流模式邏輯的異同。分別就速度、扇出能力及雜訊邊限等各方面的特性，比較分析模擬後的結果。 在相同的製程技術下，電流比值邏輯比電流模式邏輯約快20%，扇出能力改善約5—10倍，同時在D型起伏器中的設定時間，比原來快了4倍左右。凡此種種，顯示其基本的邏輯性能，改善了許多。但因其增益不足為1，經過幾級串接後，必須加一級增益級，以恢復被衰減的電流比值，同時維護它的雜訊邊限能力。 本研究使用雙載子互補金氧半導體(Bi-CMOS)製程，射極尺寸為1.5μmx4μm的技術。一起把電流比值邏輯及電流模式邏稱做在同一個晶片上，做為比較驗證之用。

A new logic structure, named the Current Ratio Logic (CRL), is proposed in this thesis. CRL is replacing the resistor loading of typical Current Mode Logic (CML) with a diode. And it is operated on current ratio levels instead of voltage levels. The principle of CRL will be discussed in this paper. Comparisons of logical features are made against typical CML. Summary with SPICE simulation results such as speed, fan-out, and noise margin are shown in tables and figures. Under the same processing condition, the speed of CRL is improved by about 20%, and the driving capability becomes about 5-10 times stronger over typical CML. And a D Flip-Flop using CRL concept has a set-up time 4 times better than a conventional CML D Flip-Flop. But the gain of CRL is less than 1. In multi-stages situation, the current ratio will degrade along the cascading CRL stages. A gain stage is needed to restore the correct signal current ratio. The data in the CRL D-Latch, for the same reason, will not operate properly. If a small resistor is connected in series with the loading diode, making the gain greater than 1, then the latch can hold data in normal operation. A test chip with CRL and CML circuits is built with the bipolar portion of a 1.5μmx4μm emitter feature size Bi-CMOS process.