自動化電晶體尺度設計之電腦輔助設計程式

Abstract

In this thesis, based upon the s-domain analysis, physical timing models for CMOS logic gates are developed. In deriving the models, the complete large-signal equivalent circuit of CMOS logic gates are constructed first and region-by-region linearized according to the operating regions of each Modified-Domminant-Pole-Dominant-Zero （MDPDZ） method for short-channel CMOS logic gates, the effective dominant pole in each region is found and the waveform function of the output voltage is approximated by a single-pole response. Finally, rese/fall times and delay times and delay times are formulated. The developed physical timing models is also applied to characterizing the timing models of the locally feedback gate （S/R latch）. As compared with SPICE simulation and experimental results, it is found that the maximum error of the developed timing models is confined to be within 35% for long -channel CMOS logic gates (inverters and NAND/NOR gates) and 15% for short-channel CMOS logic gates (inverters and NAND/NOR gates), respectively. The models caan also be applied to CMOS logic gates with different channel dimensions, capactive loads, device parameters, and input excitations. Much better accuracy can be obtined for logic gates with commonly-used channel dimensions or large capacitive load. The developed timing models are also applied to investigate the speed feature of the CMOS logic gates in device scaling. It is seen that the quasi-constant-voltage scaling law has an optimal figure of merit in speed, area, and reliability. In addition, the optimal width ratio of small-geometry CMOS inverters depends on the ratio of effective channel modulation factors rather than that of mobilities. Based upon the developed timing models, a new sizing approach is proposed, which uses the transition times of the logic gae as the design parameters. Using this approach, the Near-Characteristic-Waveform-Synthesizing-Method (NCWSM) is proposed to determine the device sizes of CMOS combinational logic circuits from a rise (or fall) time so that the internal waveforms are near to the characteristic waveform. By using the NCWSM, a fixed-delay sizing algorithm is developed, which sizes the CMOS combinational logic circuit quickly and globally. It is shown that the fixed-delay sizing using the NCWSM has a high computation efficiency and a low CPU-time complexity. Besides, as the fixed-delay specification is near the minimum total delay time, the circuit sized by the NCWSM has a better performance in both chip area and power consumption compared to the heuristic approach. A method called Optimal-Characteristic-Waveform-Synthesizing-Mothod (OCWSM) is also proposed, which calculates the optimal rise/fall time to achieve the minimum reachable delay time while retaining the waveforms to be characteristic. By using transition times (rise and fall times) of each gate as the variables of the optimization process and by using the OCWSM to obtain the initial guess of the optimization process, a new optimization process is proposed and implemented. It has been shown that the optimization process with these two considerations can realize a smaller fixed-delay specification than that in the conventional approaches. Moreover, the optimization results of the process with these two considerations is better than those in the conventional approaches. A experimental program for the sizing of the CMOS combinational logic circuit, called the TISA (Timing Synthesis and Analysis), is then constructed by using the developed physical timing models, sizing methodologies, and sizing algorithms. Using the TISA, the device sizes of each gates within the logic circuit can be designed and then the signal timing of the design circuit can be verified. The required computer time and memory space are quite small and the error in the signal timing is tolerable, as compared with SPICE simulations. Ther5efore, the TISA program has a promising feature in future VLSI design . 本論文首先提出以頻率響應的範圍分析互補式金氧半組合邏輯閘的轉換時間，應用主 極點主零點方法（對長通道的互補式金氧半組合邏輯閘）及修飾的主極點主零點方法 （對短通道的互補式金氧半組合邏輯閘），解決多極點多零點的問題，而建立互補式 金氧半組合邏輯閘的序模式．經由電路模擬器（SPICE ）的驗證後，在不同的通道尺 寸，電容負載，製程參數，及輸入波形下，所發展建立的互補式金氧半邏輯閘的時序 模式，對長通道而言，最大誤差為35％，對短通道而言，最大誤差為15％．對常用的 通道尺寸或大的電容負載而言，誤差可再縮小．而所花費的計算機時間祇有百分之一 ．同時，應用發展完成的時序模式，可以描述互補式金氧半邏輯閘在未來超大型積體 電路的縮小法則下所具有的速度特質． 其次，本論文提出，以邏輯閘的上升╱下降時間，作為設計參數的尺寸設計方式，並 且發展近特性波形合成法（NCWSM ）來計算整個電路的通道尺寸．應用近特性波形合 成法，可以建立了最佳特性波形合成法（OCWSM ），固定延遲時間的尺寸設計演繹法 都有較優異的表現． 利用發展完成的時序模式，設計法則，及尺寸設計演繹法，建立一個電腦輔助自動化 設計程式－TISA，這個程式可以根據輸入的邏輯電路及電晶體的尺寸來分析電路的時 序，或者，根據輸入的邏輯電路及電路的延遲時間來求得電晶體的尺寸，所需要的電 腦時間與記憶體容量都遠小於SPICE ．因此，TISA在未來的超大型積體電路自動化設 計中，具備高度的發展潛力．