標題: | A comparison of plasma-induced damage on the reliability between high-k/metal-gate and SiO(2)/poly-gate complementary metal oxide semiconductor technology |
作者: | Weng, Wu-Te Lee, Yao-Jen Lin, Horng-Chih Huang, Tiao-Yuan 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 1-四月-2010 |
摘要: | This study examines the effects of plasma-induced damage (PID) both on advanced SiO(2)/poly-gate and Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO(2)/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high-k/metal-gate CMOS technology. (C) 2010 Elsevier Ltd. All rights reserved. |
URI: | http://dx.doi.org/10.1016/j.sse.2010.01.007 http://hdl.handle.net/11536/5606 |
ISSN: | 0038-1101 |
DOI: | 10.1016/j.sse.2010.01.007 |
期刊: | SOLID-STATE ELECTRONICS |
Volume: | 54 |
Issue: | 4 |
起始頁: | 368 |
結束頁: | 377 |
顯示於類別: | 期刊論文 |