LOCOS閘極結構次微米金氧半元件的模式研究

Abstract

本論文發展出一套新方法可供分析窄通道金氧半元件的臨界電壓和汲極電流特性。這套新模式適用於窄通道和LOCOS閘極場離氧化結構的次微米金氧半元件，尤其是基片具有非均勻雜質分佈結構的元件。 我們在臨界電壓的模式裡採用步階近似法來模擬閘極氧化層下的雜質分佈，而推尋臨界電壓的模式時並沒有假設鳥嘴下的空乏區深度和位置為線性關係，也是首次把鳥嘴下的場佈植擾動和通道佈植影考慮在臨界壓公式裡。臨界電壓公式的推導包括兩部分，一是由計算鳥嘴電容來函蓋邊緣的場效應，以及由一維poisson公式來函蓋工作在不同基片偏壓(back gate bias)的通道佈植和場佈植的效應。藉著SIMS和SRP量測值的校正，可以由 SUPREM IV模擬出準確的通道雜質分佈。如此方能夠準確預估大範圍的基片偏壓和閘極寬度的臨界電壓值。 本論文亦首次的推導出窄通金氧半元件的次臨限區域汲極電流解析式，它包含二維電場所導致的窄通道效應，尤其是次臨限電流的斜率和softening特性亦可輕由解析式推導出來。在大範圍的基片偏壓和閘極寬度下，解析公式計算出的值與實驗值甚為符合。這此發展出的解析模式對目前超大型和極大型金氧半元件的設計有莫大的幫助。

In this thesis, a new approach to the modeling of the threshold voltage and drain current characteristics in narrow gate width MOS devices has been developed. The developed models are suitable for submicron MOS devices with narrow gate width and LOCOS gate field oxide structure and particularly for devices with nonuniformly doped structure. The expression of the threshold voltage has been developed without the assumption of linear depletion depth under bird's beak. The model for the field implant encroachment and double implants beneath bird's beak is included in the threshold voltage model for the first time. It was derived by modeling the bird's beak cpacitance to include the fringing field effect and solving Poisson 1-D equation to include the channel implant and field implant effects at different operating back gate biases. Accurate channel profile has been obtained from SUPREM IV and calibrated against those measured data b SIMS and SRP. This allows excellent ageement between the modeled and experimentally measured results of the threshold voltage for a wide range of back gate biases and gate widths. An analytical model of the subthreshold drain current model for narrow gate width MOS devices is also developed for the first time, in which the two-dimensional field induced narrow gate effect has been incorporated. In particular, the subthereshold slope and associated softening characteristics have been developed analytically. Good agreements between the modeled data and experimental data have also been achieved for a wide range of gate widths and biases. The developed models are very useful for the current VLSI or ULSI MOS device design.