標題: | A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC |
作者: | Chung, Yung-Hui Wu, Jieh-Tsorng 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Analog-digital conversion;calibration;comparators (circuits);subranging ADC;two-step ADC |
公開日期: | 1-十一月-2010 |
摘要: | A 10-bit 100-MS/s two-step ADC was fabricated using a 90 nm CMOS technology. To reduce power consumption, the ADC uses latch-type comparators for signal digitalization and an open-loop amplifier for residue amplification. The accuracy of the comparators is improved by offset calibration. The gain accuracy and the linearity of the residue amplifier are enhanced by digital background calibration. The ADC consumes 6 mW from a 1 V supply. Measured SNR and SFDR are 58.2 dB and 75 dB respectively. Measured ENOB is 9.34 bits. The FOM is 100 fJ . V per conversion-step. |
URI: | http://dx.doi.org/10.1109/JSSC.2010.2063590 http://hdl.handle.net/11536/5679 |
ISSN: | 0018-9200 |
DOI: | 10.1109/JSSC.2010.2063590 |
期刊: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Volume: | 45 |
Issue: | 11 |
起始頁: | 2217 |
結束頁: | 2226 |
顯示於類別: | 會議論文 |