可自我診斷的內建自我測試電路記憶體設計

Abstract

本論文提出能用於內嵌式隨取記憶體之自我診斷內建自我測試隨取記 憶體結構，此結構在極少的硬體負擔下，達到自我診斷的能力。在隨取記 憶體正常運作狀況下，此自我測試結構對速度性能方面降低極少。本設計 採用兩組可以偵測大部份錯誤模式的測試型量，以增快自我測試與診斷的 速度。有了自我診斷能力後，自我測試隨取記憶體的設計就能結合自我修 護容錯設計,以增加內嵌式隨取記憶體的良率。 In this thesis, a self-diagnostic BIST RAM structure for the embedded RAM which achieves the self-diagnostic capability with only a minimal overhead is proposed. The BIST structure degrades a little on the speed performance of the RAM in normal operation. Two sets of test patterns which can detect most of the models of failures are adopted to speed up the self-testing and diagnosis. With self-diagnosis capability, this BIST RAM design can be incorporated with the self-repaired redundant design to increase the yield of the embedded RAM.