液相沉積閘極絕緣層之複晶矽薄膜電晶體的低溫製作

Abstract

利用複晶矽薄膜電晶體同時將畫素電晶體以及周邊驅動電路積體化於大面 積玻璃基座, 已是平面液晶顯示器的重要技術之一, 而低溫研製複晶矽薄 膜電晶體將是未來的技術主流．本研究群首度嘗試將室溫下液相沉積成長 的二氧化矽應用在複晶矽薄膜電晶體的閘極氧化層, 成功地建立高特性複 晶矽薄膜電晶體的低溫製程條件．為了解決複晶矽薄膜電晶體的漏電流問 題, 本文探討了漏電流的傳導機制, 並嘗試以一新的"自引發低濃度汲 極" 的結構, 與薄化複晶矽層的方法, 來改善漏電流的問題．結果顯示, 此方法所製造的複晶矽薄膜電晶體可將漏電流降至每微米通道 (channel width) 寬小於 0.1 pA 的程度, 而開關電流比 ( ON/OFF current ratio) 可大於十的七次方, 而且幾忽不受閘極電壓與汲極電壓的影響． Active-matrix liquid-crystal displays (AMLCDs) with on-glass peripheral circuits made from poly-Si TFT's are one of the most promising technologies for full-color flat-panel display. In this research, high performance poly-Si TFT's with liquid- phase- deposition SiO2 as gate insulators have been successfully fabricated by an entirely low temperature process (< 625 C) in order to utilized large-area glass substrate. OFF- state current mechanisms have been clarified which are helpful to find out the accurate solution for reducing OFF-state current. Attempts have been made to produce a self-induced lightly-doped-drain (SI-LDD) structure and to thin the active poly-Si films in an effort to reduce the OFF-state current. The low leakage current (less than 0.1 pA per um of channel width) of poly-Si TFT's with excellent ON/OFF current ratio (larger than 7 order) independent of gate voltage and drain voltage have been also obtained.