高速管線式RS(255,239)解碼器的超大型積體電路實現

Abstract

因為能獲得高速的效果, 管線式架構已被廣泛的用於設計RS解碼器.在文 獻中有些解碼器架構已被發表, 他們使用管線式架構並且以符號脈衝作為 系統脈衝, 其結果是系統脈衝週期大於三倍乘法時間.在本文中, 藉由分 割解碼程序的方法, 提出一個修正過的架構, 將使得系統脈衝週期降到接 近一個乘法時間. 亦即, 資料傳輸率將被提高到比一般架構快接近三倍. Berlekamp-Massey 的理論與一個修正過的 Forney的理論被用來解錯誤 位址多項式與錯誤值.一個單晶片RS(255,239) 解碼器被以零點八微米技 術完成, 晶片面積為五點八釐米乘五點八釐米, 包含約十四萬個電晶體, 使用一個外接的重設控制信號與單相的系統脈衝, 晶片的延遲是1024個系 統脈衝週期時間. Pipelined structure has been widely used to implement high speed RS decoder. There are a few decoder structures published in the literature with the period of system clock is longer than 3 multiplication time which use symbol clocks as system clocks and pipelined structure is adopted. In this thesis, a modified structure is presented to reduce the length of system clock period. The data rate can be as high as near 3 times of that used in traditional structure. Berlekamp-Massey's algorithm and a modified Forney's algorithm are chosen to evaluate error location polynomial and error value. Using the modified structure, a single chip RS(255,239) decoder is implemented using 0.8um technology, with chip area 5.8mm by 5.8mm, containing about 140000 transistors. One external reset control signal and one single phase system clock used. The latency for this chip is 1024 clock cycles.