最佳化之座標旋轉演算法及其架構設計

Abstract

在本論文中，提出具有高輸出率的管線化架構，來實現座標旋轉演算法。 由於座標旋轉演算法的運算須視剩餘旋轉角度或Ｙ軸分量的正負而定，此 為座標旋轉演算法先天性循序關係的限制，影響座標旋轉演算法的運算速 度。在座標旋轉演算法中，剩餘旋轉角度或Ｙ軸分量總是必須逼近到零， 因此我們若對剩餘旋轉角度或Ｙ軸分量取絕對值，則其運算變成固定之減 法運算，使其逼近到零。如此可將座標旋轉演算法中角度的運算和旋轉的 運算分開，解除了座標旋轉演算法中先天性的循序關係，可提升座標旋轉 演算法的運算速度。根據上述取絕對值的運算，加上管線化的架構，我們 使用最大位先出之符號數絕對值運算，可非常快速且正確地處理符號判斷 ，大大地提升了座標旋轉演算法的運算速度。根據我們所提出的架構，在 經過第一次角度運算或旋轉之後，每隔２或３個時鐘週期，即可判斷出一 個剩餘旋轉角度或Ｙ軸分量的符號。其中管線片段僅包含一個或兩個符號 數加法器和一個數字的絕對值運算單元，一個管線片段可在非常短的時間 內完成，所以其運作頻率非常高，具有高的輸出率，又具有相當的規則性 ，非常適合ＶＬＳＩ的實現。我們以０．８ｕｍＣＭＯＳ之技術來實現座 標旋轉演算法中旋轉模式的循序架構，晶片面積為 ６．２ｍｍ Ｘ５． ３ｍｍ，資料運算元長度為３２位元，具有２４位元的精確度，約有１８ ０００個電晶體，工作頻率為１０ＭＨｚ。 In this thesis, efficient pipelined, high throughput rate architectures for CORDIC algorithm are presented. Since the CORDIC operation is dependent on the sign of remaining rotation or the component of Y-axis, the computation time of the CORDIC algorithm is limited by its inherently sequential relationship. However, in CORDIC algorithm, the remaining rotation angle or Y- component are always required to approach to zero. The key idea of our approach is to separate the sign detection operation of remaining rotation angle or the component of Y- axis evaluation from the rotation operation. By taking the absolute values of these variables, the angle or Y-component iteration are fixed to subtraction operation. Therefore, we can successively subtract the residues without knowing the signs of preceding remaining rotation angle or the component of Y-axis, while their signs can be detected parallely, independently and in a pipelined fashion. Doing this way the sequential relationship of CORDIC algorithm between the computation of angle calculated and rotation operation is eliminated, and the time for the CORDIC operations can be greatly reduced. The corresponding CORDIC processor we proposed consists of regular pipelined slices. Each pipeline slice contains only one or two signed-digit adder and one digit level absoluter. Therefore, the duration of a clock cycle is very short, that is about two or three signed-digit adder delays. And iteration is completed within two or three clock cycles. Since the pipeline slice is regular, the CORDIC processor is well suited for VLSI implementation. The sequential architecture for rotation mode of CORDIC algorithm is realized by 0.8um CMOS technology to verify our design. The chip, which has 32-bit operand wordlength, is 6.2mm*5.3mm in area. It can operate at 10MHz clock frequency.