電流式類比數位轉換器之設計與實現

Abstract

在此論文中,主要是探討電流式類比數位轉換器之設計與實現。在此設計 中，所要處理的訊號是電流而非電壓。在所提之演算式類比數位轉換器中 ，我們利用主動式電流鏡來降低通道長度調變效應，並利用密勒電容及 dummy開關來降低取樣儲存電路之clock feed-through效應，我們並設計 了一個高線性號電壓電流轉換器。由HSPICE模擬，此電流式類比數位轉換 器可達到10個位元，250kHz的取樣律，除了電路設計外，我們並作了IC佈 局並交CIC生產。從設計中我們發現上述之電路之速度未臻理想，我們在 論文中也提了互補式單元，及利用"super MOS"電流鏡來作改善，這種作 法主要的優點是能得到合理的準確性而不須加長通道的長度與寬度，因此 可獲得較高速演算式類比數位轉換器。由HSPICE模擬，可達到6個位元 ，30MHz的取樣律。 This thesis deals with the design and implementation of an current-mode A/D converter. The analog signals to be processed are currents instead of voltages. In this algorithmic A/D conveters, we use the active current mirror to reduce channel- length-modulation effects. We design a sample-and-hold (S/H) circuits to reduce clock feedthrough effects by Miller hold capacitors and a dummy switch. The other component in this thesis is a high linearity voltage-to-current(OTA) transducer. From HSPICE simulations, 10 bits current-mode A/D converters can operate at 250kHz sampling rate. Moreover, we latout this design and fabricated into chip through CIC(Chip Implementation Center). From the design, we found that the speed of algorithmic current-mode A/D converters is not fast enough. In the thesis, complementary(P and N type) cells areproposed. We modified this complementary cells by "super MOS" current mirror. The main benefit of "super MOS" mirror is to get reasonable accuracy without increasing channel lehgth and width. For this reason, higher speed current-mode A/D converters are achieveable by the algorithmic method. From HSPICE simulations, the "super MOS" A/D converter operates at 30MHz with 6-bit resolution in this thesis.