奇異數分解處理器之架構設計與硬體製作

Abstract

矩陣的奇異數分解是信號處理中非常重要的一種運算方法，由於它的計算 複雜，因此，速度的提昇便受限於硬體的架構設計與製作。研究奇異數分 解處理器的動機便起源於如何以最有效的架構做最快速的硬體運算。在本 篇論文中，我們發展了一個以2x2 矩陣為基本運算單元的架構，來做最大 到16x16 矩陣的奇異數分解。這個架構不但快速，而且簡單，非常適合於 硬體的製作。我們使用此架構做了一顆100 腳的積體電路以驗證其正確性 ，它共有12383 個邏輯閘，使用0.8 微米 CMOS 製程，僅佔佈局面積 4610x5320平方微米，速度可高達 50MHz。在線路模擬上，我們使用 4個2 x2 處理器做4x4 矩陣的奇異數分解，驗證結果證明，這顆積體電路不但 正確，而且快速，可以滿足高速的奇異數分解需求。 The Singular Value Decomposition (SVD) of a matrix is an important numerical algorithm for signal processing. Because it is complex and difficult for SVD computation, efficient hardware architecture and implementation are indispensable when real-time computation of the SVD is required. In this thesis, a novel hardware oriented diagonalization scheme for the SVD of an expandable 2x2 matrix, the basic step for the computation of the SVD, was presented. This architecture can perform very fast SVD computation and is very simple for ease in hardware implementation. A VLSI implementation of this architecture has been developed . The processor chip is realized as a standard cell design with 12383 gates in 0.8u SPDM CMOS technology, 50 MHz clock frequency, and 4610u x 5320u silicon area in a 100-pin package. Simulation for SVD of a 4x4 matrix, which is constructed by using four 2x2 SVD processor, has also been done as part of verification.