標題: 多工作線處理器線間通訊與同步之整合性支援
Integrated Support to Improve Inter-Thread Communication and Synchronization in a Multithreaded Processor
作者: 陳俊旭
Chiun-Shiu Chen
曾建超
Chien-Chao Tseng
資訊科學與工程研究所
關鍵字: 多工作線;通訊;同步;平行度;超純量;通訊方法;暫存器快取記憶體;Multithreading;Communication;Synchronization;Parallelism; Superscalar;Communication Scheme
公開日期: 1993
摘要: 本論文提出一個整合編譯器, 執行時間控制(Runtime Control),和硬體支 援等三方面的方法, 來增進多工作線(Multithreaded)處理器線間通訊( Communication)與同步(Synchronization)之效能. 多工作線( Multithreading)能藉由提供及開發更多的程式平行度(Parallelism)以供 執行的方式, 來增加處理器之使用效率.然而, 此使用效率的增加幅度受 限於線間的通訊與同步問題, 而這些問題會導致一個多工作線系統的效能 不彰. 所以, 我們希望能在一具有多工作線能力之超純量(Superscalar) DLX處理器上,提出有效率的線間通訊與同步的方法. 此外, 對於這些方法 我們將從編譯器, 執行時間控制和硬體等三方面來討論所需的支援.最 後, 我們會以實際的模擬來驗證與評估這些方法之優劣. This thesis suggests an integrated compiler, runtime control, and hardware solution to improve inter-thread communication and synchronization in a multithreaded processor architecture. Multithreading improves processor utilization by supporting and exphoiting more parallelism. The improvement of utilization, however, meets a great hindrance in inter-thread communication and synchronization problems. These problems incur extra communication overheads and thus cause the performance degradation in a multithreading system. In this thesis, we will propose efficient inter-thread communication and synchronization schemes based on a superscalar DLX processor with multithreading functionality. These schemes will be discussed from viewpoints of compiler, runtime control, and hardware supports. We also give the simulation result to show the correctness and effectiveness of the proposed schemes.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT820392017
http://hdl.handle.net/11536/57820
Appears in Collections:Thesis