應用於靜態隨機存取記憶體之複晶矽薄膜電晶體之研究

Abstract

本文針對補償結構所製成之複晶矽薄膜電晶體特性來進行研究。一個介於 閘極與汲極之間的少量離子佈植區被用以降低汲極漏電流。我們得到最佳 化的離子佈植劑量及補償長度使得薄膜電晶體之反常漏電流被有效地降低 並且與閘極電壓無關。利用 0.6 微米的純質補償長度及爐管氫化可得到 0.4 pA/微米的低漏電流及 2E7 的開閉電流比。經過電漿鈍化處理後，可 得到 0.005 pA/微米的低漏電流及 1E8的開閉電流比。此結構只須加上一 小段的補償長度即可有效地降低薄膜電晶體之反常漏電流，而且能保持高 的導通電流，利用此簡單的結構與電漿處理能有效地改善薄膜電晶體特性 ，使其更適於高密度靜態隨機存取記憶體之應用。 A simple device structure called the offset structure was investigated to improve the electric characteristics of p- channel polysilicon TFT's. A lightly doped region was introduced between the gate edge and the drain as a buffer region. We optimized the dopant concentration and the length in the offset region to reduce the electric field along the channel, which decreased the anomalous leakage current of a conventional TFT. It resulted in the leakage current virtually independent of the gate voltage Vg. A high on-current could also be obtained in the optimum condition. Low leakage current of 0.4 pA/um and high on/off-current ratio of 2E7 were obtained by using a 0.4 um undoped offset with a furnace hydrogenation. In addition,the short-channel effect was greatly reduced by the offset structure. Two hydrogenation methods, the furnace and plasma hydrogenation, were also studied. Plasma passivated TFT' s show superior characteristics than the furnace hydrogenated ones. After plasma passivation for 2 hr, the leakage current of 0.005 pA/um and high on/off-current of 1E8 were achieved with an 0.6 um undoped offset.