關止狀態應力引致金氧半電晶體性能之劣化

Abstract

本論文提出藉由關止狀態之應力來觀察金氧半電晶體元件性能之衰壞情況 ﹒為了能充分了解元件劣化的物理機構，各種元件之參數被適當地萃取出 以便用來作合理的解釋﹒經由應力將會產生表面或氧化層中的陷阱，造成 電子或電洞在矽表面或氧化層中被捕獲﹒在本論文中，除了主題環繞在劣 化的物理來源外，一些重要之元件參數亦被提出以說明隨時間變化而導致 的衰壞情況﹒上述的研究將能幫助我們對於金氧半電晶體的可靠性問題求 得更深一層的了解﹒ The thesis presents new observations of performance degradation in p-channel MOSFET devices under off-state stress. In order to establish the physical mechanisms responsible for device degradation, important transistor parameters have been extracted, some of which can be regarded as a degradation monitor. The stress generates the interface traps and/or oxide trapping, resulting in the capture of electrons or holes in the silicon interface and/or oxide. In this thesis, in addition to addressing the physical mechanisms, we also imploy important device parameters based on which the time-dependent performance degradation model has been established. This study can improve current understanding of the hot-carrier induced degradation in submicron MOSFET's.